| Integrated circuit design changes using through-silicon vias H Barowski, J Keinert, SH Rangarajan, H Ren, S Saha US Patent 9,501,603, 2016 | 32 | 2016 |
| Path-based congestion reduction in integrated circuit routing H Folberth, S Peyer, S Saha US Patent 9,384,316, 2016 | 10 | 2016 |
| Hierarchical wire-pin co-optimization CJ Berry, AKM Chandrasekaran, RJ Darden, S Ramji, S Saha US Patent 9,715,572, 2017 | 8 | 2017 |
| Early scenario pruning for efficient design space exploration in physical synthesis M Anwar, S Saha, MM Ziegler, L Reddy 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | 8 | 2016 |
| Layout of large block synthesis blocks in integrated circuits H Barowski, HD Folberth, J Keinert, S Saha US Patent 9,910,948, 2018 | 7 | 2018 |
| Integrated circuit design changes using through-silicon vias H Barowski, J Keinert, SH Rangarajan, H Ren, S Saha US Patent 9,569,580, 2017 | 7 | 2017 |
| Layout of large block synthesis blocks in integrated circuits H Barowski, HD Folberth, J Keinert, S Saha US Patent 10,534,884, 2020 | 6 | 2020 |
| Layout of large block synthesis blocks in integrated circuits H Barowski, HD Folberth, J Keinert, S Saha US Patent 9,928,329, 2018 | 6 | 2018 |
| Constraint-driven pin optimization for hierarchical design convergence CJ Berry, RJ Darden, AR Jatkowski, JJ Palumbo, S Ramji, S Saha, ... US Patent 9,858,377, 2018 | 6 | 2018 |
| Boundary based power guidance for physical synthesis P Chakrabarti, K Guha, RH Nigaglioni, S Saha US Patent 9,286,428, 2016 | 6 | 2016 |
| Slack redistribution for additional power recovery CJ Berry, YH Chan, AA Mets, C Nagarajan, RH Nigaglioni, S Saha, ... US Patent 9,684,751, 2017 | 5 | 2017 |
| Physical aware technology mapping in synthesis CJ Berry, P Chakrabarti, LN Reddy, S Saha US Patent 9,443,048, 2016 | 5 | 2016 |
| Slack redistribution for additional power recovery CJ Berry, YH Chan, AA Mets, C Nagarajan, RH Nigaglioni, S Saha, ... US Patent 9,734,268, 2017 | 4 | 2017 |
| Timing constraints formulation for highly replicated design modules C Ravindranath, S Saha, R Srinidhi US Patent 9,703,923, 2017 | 4 | 2017 |
| Congestion aware layer promotion CJ Berry, L Reddy, S Saha US Patent 9,514,265, 2016 | 4 | 2016 |
| Congestion aware layer promotion CJ Berry, L Reddy, S Saha US Patent 9,495,502, 2016 | 4 | 2016 |
| Layout of large block synthesis blocks in integrated circuits H Barowski, HD Folberth, J Keinert, S Saha US Patent 10,242,140, 2019 | 3 | 2019 |
| Layout of large block synthesis blocks in integrated circuits H Barowski, HD Folberth, J Keinert, S Saha US Patent 10,235,487, 2019 | 3 | 2019 |
| Circuit placement with electro-migration mitigation HD Folberth, DA Kumar, S Peyer, S Saha, H Shaik US Patent 9,536,037, 2017 | 3 | 2017 |
| Physical aware technology mapping in synthesis P Chakrabarti, CJ Berry, LN Reddy, S Saha US Patent 9,443,047, 2016 | 3 | 2016 |
