Hardware implementation of finite-field arithmetic JP Deschamps McGraw-Hill, Inc., 2009 | 199 | 2009 |
Efficient elliptic curve point multiplication using digit-serial binary field operations GD Sutter, JP Deschamps, JL Imaña IEEE Transactions on Industrial Electronics 60 (1), 217-225, 2012 | 184 | 2012 |
Modular multiplication and exponentiation architectures for fast RSA cryptosystem based on digit serial computation GD Sutter, JP Deschamps, JL Imana IEEE Transactions on industrial electronics 58 (7), 3101-3109, 2010 | 103 | 2010 |
Bit-parallel finite field multipliers for irreducible trinomials JL Imaña, JM Sanchez, F Tirado IEEE Transactions on Computers 55 (5), 520-533, 2006 | 67 | 2006 |
Low complexity bit-parallel multipliers based on a class of irreducible pentanomials JL Imana, R Hermida, F Tirado IEEE transactions on very large scale integration (VLSI) systems 14 (12 …, 2006 | 35 | 2006 |
Efficient hardware arithmetic for inverted binary ring-lwe based post-quantum cryptography JL Imana, P He, T Bao, Y Tu, J Xie IEEE Transactions on Circuits and Systems I: Regular Papers 69 (8), 3297-3307, 2022 | 27 | 2022 |
Fast bit-parallel binary multipliers based on type-I pentanomials JL Imana IEEE Transactions on Computers 67 (6), 898-904, 2017 | 26 | 2017 |
Efficient Hardware Implementation of Finite Field Arithmetic for Binary Ring-LWE Based Post-Quantum Cryptography J Xie, P He, X Wang, JL Imana IEEE Transactions on Emerging Topics in Computing 10 (2), 1222-1228, 2021 | 23 | 2021 |
LFSR-Based Bit-Serial Multipliers Using Irreducible Trinomials JL Imana IEEE Transactions on Computers 70 (1), 156-162, 2020 | 21 | 2020 |
Low LatencyPolynomial Basis Multiplier JL Imaña IEEE Transactions on Circuits and Systems I: Regular Papers 58 (5), 935-946, 2010 | 20 | 2010 |
High-Speed Polynomial Basis Multipliers Overfor Special Pentanomials JL Imaña IEEE Transactions on Circuits and Systems I: Regular Papers 63 (1), 58-69, 2015 | 19 | 2015 |
Efficient polynomial basis multipliers for type-II irreducible pentanomials JL Imana IEEE Transactions on Circuits and Systems II: Express Briefs 59 (11), 795-799, 2012 | 17 | 2012 |
Low complexity bit-parallel polynomial basis multipliers over binary fields for special irreducible pentanomials JL Imana, R Hermida, F Tirado Integration 46 (2), 197-210, 2013 | 13 | 2013 |
Streaming potential across cation-exchange membranes in methanol–water electrolyte solutions VM Barragán, C Ruiz-Bauzá, JL Imaña Journal of colloid and interface science 294 (2), 473-481, 2006 | 13 | 2006 |
Effect of an AC perturbation on a desalination electrodialysis process VM Barragán, CR Bauzá, JL Imaña Desalination 142 (3), 235-244, 2002 | 6 | 2002 |
Método de multiplicación canónica sobre campos GF (2m) generados por AOPs orientado a hardware reconfigurable JL Imaña, J Sánchez, M Fernández II Jornadas sobre Computacion Reconfigurable y Aplicaciones JCRA2002, 1-6, 2002 | 6 | 2002 |
Low-delay FPGA-based implementation of finite field multipliers JL Imaña IEEE Transactions on Circuits and Systems II: Express Briefs 68 (8), 2952-2956, 2021 | 5 | 2021 |
High-throughput architecture for post-quantum DME cryptosystem JL Imaña, I Luengo Integration 75, 114-121, 2020 | 5 | 2020 |
Aplicación de campos de Galois a la verificación probabilística de funciones booleanas y métodos de multiplicación sobre campos de extensión GF (2m) J Imaña Universidad Complutense de Madrid, España, 2004 | 5 | 2004 |
Optimized reversible quantum circuits for multiplication JL Imaña Quantum Information Processing 20, 1-15, 2021 | 4 | 2021 |