| Branch-and-bound placement for building block layout H Onodera, Y Taniguchi, K Tamaru Proceedings of the 28th ACM/IEEE Design Automation Conference, 433-439, 1991 | 172 | 1991 |
| Operational-amplifier compilation with performance optimization H Onodera, H Kanbara, K Tamaru IEEE Journal of solid-state circuits 25 (2), 466-473, 1990 | 146 | 1990 |
| Refractive-index measurement of bulk materials: prism coupling method H Onodera, I Awai, J Ikenoue Applied optics 22 (8), 1194-1197, 1983 | 135 | 1983 |
| A cyclic A/D converter that does not require ratio-matched components H Onodera, T Tateishi, K Tamaru IEEE Journal of Solid-State Circuits 23 (1), 152-158, 1988 | 88 | 1988 |
| A low-power and area-efficient radiation-hard redundant flip-flop, DICE ACFF, in a 65 nm thin-BOX FD-SOI K Kobayashi, K Kubota, M Masuda, Y Manzawa, J Furuta, S Kanda, ... IEEE Transactions on Nuclear Science 61 (4), 1881-1888, 2014 | 86 | 2014 |
| An area-efficient 65 nm radiation-hard dual-modular flip-flop to avoid multiple cell upsets R Yamamoto, C Hamanaka, J Furuta, K Kobayashi, H Onodera IEEE Transactions on Nuclear Science 58 (6), 3053-3059, 2011 | 82 | 2011 |
| A performance optimization method by gate sizing using statistical static timing analysis M Hashimoto, H Onodera Proceedings of the 2000 international symposium on Physical design, 111-116, 2000 | 71 | 2000 |
| An efficient algorithm for layout compaction problem with symmetry constraints R Okuda, T Sato, H Onodera, K Tamariu 1989 IEEE International Conference on Computer-Aided Design, 148,149,150,151 …, 1989 | 71 | 1989 |
| A statistical gate-delay model considering intra-gate variability K Okada, K Yamaoka, H Onodera ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003 | 69 | 2003 |
| Estimation of propagation delay considering short-circuit current for static CMOS gates A Hirata, H Onodera, K Tamura IEEE Transactions on Circuits and Systems I: Fundamental theory and …, 1998 | 64 | 1998 |
| Wide-supply-range all-digital leakage variation sensor for on-chip process and temperature monitoring AKMM Islam, J Shiomi, T Ishihara, H Onodera IEEE Journal of Solid-State Circuits 50 (11), 2475-2490, 2015 | 60 | 2015 |
| A 65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop capable of protecting soft errors on the C-element J Furuta, C Hamanaka, K Kobayashi, H Onodera 2010 Symposium on VLSI Circuits, 123-124, 2010 | 60 | 2010 |
| Variation-sensitive monitor circuits for estimation of global process parameter variation IAKM Mahfuzul, A Tsuchiya, K Kobayashi, H Onodera IEEE Transactions on Semiconductor Manufacturing 25 (4), 571-580, 2012 | 58 | 2012 |
| A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process T Miyazaki, M Hashimoto, H Onodera ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE …, 2004 | 57 | 2004 |
| Variability: Modeling and its impact on design H Onodera IEICE transactions on electronics 89 (3), 342-348, 2006 | 53 | 2006 |
| The impact of RTN on performance fluctuation in CMOS logic circuits K Ito, T Matsumoto, S Nishizawa, H Sunagawa, K Kobayashi, H Onodera 2011 International Reliability Physics Symposium, CR. 5.1-CR. 5.4, 2011 | 51 | 2011 |
| Statistical analysis of clock skew variation in H-tree structure M Hashimoto, T Yamamoto, H Onodera Sixth international symposium on quality electronic design (isqed'05), 402-407, 2005 | 51 | 2005 |
| A statistical gate delay model for intra-chip and inter-chip variabilities K Okada, K Yamaoka, H Onodera Proceedings of the 2003 Asia and South Pacific Design Automation Conference …, 2003 | 45 | 2003 |
| Post-layout transistor sizing for power reduction in cell-based design M Hashimoto, H Onodera Proceedings of the 2001 Asia and South Pacific Design Automation Conference …, 2001 | 45 | 2001 |
| A power optimization method considering glitch reduction by gate sizing M Hashimoto, H Onodera, K Tamaru Proceedings of the 1998 international symposium on Low power electronics and …, 1998 | 44 | 1998 |
Kazutoshi KobayashiProfessor, Kyoto Institute of Technology在 kit.ac.jp 的电子邮件经过验证
