| Algorithms of finding the first two minimum values and their hardware implementation CL Wey, MD Shieh, SY Lin IEEE Transactions on Circuits and Systems I: Regular Papers 55 (11), 3430-3437, 2008 | 160 | 2008 |
| A new modular exponentiation architecture for efficient design of RSA cryptosystem MD Shieh, JH Chen, HH Wu, WC Lin IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16 (9 …, 2008 | 118 | 2008 |
| A systematic approach for parallel CRC computations MHWAS MING-DER SHIEH, CH Chen, HF Lo Journal of information science and engineering 17, 445-461, 2001 | 95 | 2001 |
| High-speed, low-complexity systolic designs of novel iterative division algorithms in GF (2/sup m/) CH Wu, CM Wu, MD Shieh, YT Hwang IEEE Transactions on Computers 53 (3), 375-380, 2004 | 75 | 2004 |
| Word-based Montgomery modular multiplication algorithm for low-latency scalable architectures MD Shieh, WC Lin IEEE transactions on computers 59 (8), 1145-1151, 2010 | 59 | 2010 |
| A new algorithm for high-speed modular multiplication design MD Shieh, JH Chen, WC Lin, HH Wu IEEE Transactions on Circuits and Systems I: Regular Papers 56 (9), 2009-2019, 2008 | 54 | 2008 |
| Efficient memory-addressing algorithms for FFT processor design HF Luo, YJ Liu, MD Shieh IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (10 …, 2014 | 49 | 2014 |
| Design of an efficient FFT processor for DAB system HF Lo, MD Shieh, CM Wu ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems …, 2001 | 49 | 2001 |
| A high-performance unified-field reconfigurable cryptographic processor JH Chen, MD Shieh, WC Lin IEEE transactions on very large scale integration (VLSI) systems 18 (8 …, 2009 | 45 | 2009 |
| Fast scalable radix-4 Montgomery modular multiplier SH Wang, WC Lin, JH Ye, MD Shieh 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 3049-3052, 2012 | 39 | 2012 |
| Systolic VLSI realization of a novel iterative division algorithm over GF (2/sup m/): a high-speed, low-complexity design CH Wu, CM Wu, MD Shieh, YT Hwang ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems …, 2001 | 33 | 2001 |
| Scalable montgomery modular multiplication architecture with low-latency and low-memory bandwidth requirement WC Lin, JH Ye, MD Shieh IEEE Transactions on Computers 63 (2), 475-483, 2012 | 30 | 2012 |
| ASLCScan: A scan design technique for asynchronous sequential logic circuits CL Wey, MD Shieh, PD Fisher Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93 …, 1993 | 30 | 1993 |
| An area-efficient versatile Reed-Solomon decoder for ADSL JC Huang, CM Wu, MD Shieh, CH Wu 1999 IEEE International Symposium on Circuits and Systems (ISCAS) 1, 517-520, 1999 | 28 | 1999 |
| VLSI architectural design tradeoffs for sliding-window log-MAP decoders CM Wu, MD Shieh, CH Wu, YT Hwang, JH Chen IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (4), 439-447, 2005 | 26 | 2005 |
| Low-complexity VLSI design of large integer multipliers for fully homomorphic encryption JH Ye, MD Shieh IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (9 …, 2018 | 25 | 2018 |
| Design and implementation of a DAB channel decoder MD Shieh, CM Wu, HH Chou, MH Chen, CL Liu IEEE Transactions on Consumer Electronics 45 (3), 553-562, 1999 | 23 | 1999 |
| Design of a high-speed square generator CL Wey, MD Shieh IEEE Transactions on Computers 47 (9), 1021-1026, 1998 | 22 | 1998 |
| Enhancing fan engagement in a 5G stadium with AI-based technologies and live streaming CW Wu, MD Shieh, JJJ Lien, JF Yang, WT Chu, TH Huang, HC Hsieh, ... IEEE Systems Journal 16 (4), 6590-6601, 2022 | 21 | 2022 |
| Low-complexity high-throughput QR decomposition design for MIMO systems JS Lin, YT Hwang, SH Fang, PH Chu, MD Shieh IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (10 …, 2014 | 21 | 2014 |
