| Surface-potential-based silicon carbide power MOSFET model for circuit simulation M Shintani, Y Nakamura, K Oishi, M Hiromoto, T Hikihara, T Sato IEEE Transactions on Power Electronics 33 (12), 10774-10783, 2018 | 32 | 2018 |
| Variation-aware hardware Trojan detection through power side-channel FS Hossain, M Shintani, M Inoue, A Orailoglu 2018 IEEE International Test Conference (ITC), 1-10, 2018 | 29 | 2018 |
| On-die parameter extraction from path-delay measurements T Takahashi, T Uezono, M Shintani, K Masu, T Sato 2009 IEEE Asian Solid-State Circuits Conference, 101-104, 2009 | 27 | 2009 |
| LSTA: Learning-based static timing analysis for high-dimensional correlated on-chip variations S Bian, M Shintani, M Hiromoto, T Sato Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 26 | 2017 |
| A simulation model for SiC power MOSFET based on surface potential Y Nakamura, M Shintani, K Oishi, T Sato, T Hikihara 2016 International Conference on Simulation of Semiconductor Processes and …, 2016 | 24 | 2016 |
| A high power curve tracer for characterizing full operational range of SiC power transistors Y Nakamura, M Shintani, T Sato, T Hikihara 2016 International Conference on Microelectronic Test Structures (ICMTS), 90-94, 2016 | 19 | 2016 |
| Measurement and modeling of gate–drain capacitance of silicon carbide vertical double-diffused MOSFET M Shintani, Y Nakamura, M Hiromoto, T Hikihara, T Sato Japanese Journal of Applied Physics 56 (4S), 04CR07, 2017 | 18 | 2017 |
| A variability-aware adaptive test flow for test quality improvement M Shintani, T Uezono, T Takahashi, K Hatayama, T Aikyo, K Masu, T Sato IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 18 | 2014 |
| An adaptive test for parametric faults based on statistical timing information M Shintani, T Uezono, T Takahashi, H Ueyama, T Sato, K Hatayama, ... 2009 Asian Test Symposium, 151-156, 2009 | 18 | 2009 |
| Organic current mirror PUF for improved stability against device aging Z Qin, M Shintani, K Kuribara, Y Ogasahara, T Sato IEEE Sensors Journal 20 (14), 7569-7578, 2020 | 16 | 2020 |
| Artificial neural network based test escape screening using generative model M Shintani, M Inoue, Y Nakamura 2018 IEEE International Test Conference (ITC), 1-8, 2018 | 15 | 2018 |
| Workload-aware worst path analysis of processor-scale NBTI degradation S Bian, M Shintani, S Morita, H Awano, M Hiromoto, T Sato Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 203-208, 2016 | 15 | 2016 |
| Small delay fault model for intra-gate resistive open defects M Arai, A Suto, K Iwasaki, K Nakano, M Shintani, K Hatayama, T Aikyo 2009 27th IEEE VLSI Test Symposium, 27-32, 2009 | 15 | 2009 |
| Nonlinear delay-table approach for full-chip NBTI degradation prediction S Bian, M Shintani, S Morita, M Hiromoto, T Sato 2016 17th International Symposium on Quality Electronic Design (ISQED), 307-312, 2016 | 13 | 2016 |
| Path clustering for adaptive test T Uezono, T Takahashi, M Shintani, K Hatayama, K Masu, H Ochi, T Sato 2010 28th VLSI Test Symposium (VTS), 15-20, 2010 | 13 | 2010 |
| Wafer-level variation modeling for multi-site RF IC testing via hierarchical Gaussian process M Shintani, M Inoue, T Nakamura, M Kajiyama, M Eiki 2021 IEEE International Test Conference (ITC), 103-112, 2021 | 12 | 2021 |
| Accurate recycled FPGA detection using an exhaustive-fingerprinting technique assisted by WID process variation modeling F Ahmed, M Shintani, M Inoue IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 11 | 2020 |
| Feasibility of a low-power, low-voltage complementary organic thin film transistor buskeeper physical unclonable function Y Ogasahara, K Kuribara, M Shintani, T Sato Japanese Journal of Applied Physics 58 (SB), SBBG03, 2019 | 11 | 2019 |
| Statistical extraction of normally and lognormally distributed model parameters for power MOSFETs H Tsukamoto, M Shintani, T Sato IEEE Transactions on Semiconductor Manufacturing 33 (2), 150-158, 2020 | 9 | 2020 |
| Recovery-aware bias-stress degradation model for organic thin-film transistors considering drain and gate bias voltages K Oshima, M Shintani, K Kuribara, Y Ogasahara, T Sato Japanese Journal of Applied Physics 59 (SG), SGGG08, 2020 | 9 | 2020 |
