| Design and analysis of PVT tolerant hybrid current starved ring VCO with bulk driven keeper technique at 45 nm CMOS technology for the PLL application M Sivasakthi, P Radhika AEU-International Journal of Electronics and Communications 173, 154987, 2024 | 9 | 2024 |
| A high-speed MCML logic gate and multiplexer design in 45 nm CMOS technology M Sivasakthi, P Radhika 2022 Fourth International Conference on Emerging Research in Electronics …, 2022 | 5 | 2022 |
| Performance comparison of MCML, PFSCL, and dynamic CML gates with parametric analysis in 45 nm CMOS technology M Sivasakthi, P Radhika Proceedings of Fourth International Conference on Communication, Computing …, 2023 | 4 | 2023 |
| Design and analysis of 7-stage MOS current mode logic power gated MOSFETs in current starved voltage-controlled oscillator for the phase locked loop application S Madheswaran, R Panneerselvam International Journal of Electrical and Computer Engineering (IJECE) 14 (02 …, 2024 | 1 | 2024 |
| Design of a high-speed MCML D-Latch at 0.6 V in 45 nm CMOS technology S Madheswaran, R Panneerselvam International Journal of Power Electronics and Drive Systems (IJPEDS) 15 (No …, 2024 | | 2024 |
| A high-speed MCML charge pump design at 10 GHz frequency in 45 nm CMOS technology for PLL application M Sivasakthi, P Radhika Analog Integrated Circuits and Signal Processing 118 (1), 49-66, 2024 | | 2024 |
