| Low-complexity high-speed decoder design for quasi-cyclic LDPC codes Z Wang, Z Cui IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15 (1), 104-114, 2007 | 198 | 2007 |
| High-throughput layered decoder implementation for quasi-cyclic LDPC codes K Zhang, X Huang, Z Wang IEEE Journal on Selected Areas in Communications 27 (6), 985-994, 2009 | 177 | 2009 |
| On finite precision implementation of low density parity check codes decoder T Zhang, Z Wang, KK Parhi ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems …, 2001 | 166 | 2001 |
| A high-speed and low-complexity architecture for softmax function in deep learning M Wang, S Lu, D Zhu, J Lin, Z Wang 2018 IEEE asia pacific conference on circuits and systems (APCCAS), 223-226, 2018 | 163 | 2018 |
| VLSI implementation issues of turbo decoder design for wireless applications Z Wang, H Suzuki, KK Parhi 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and …, 1999 | 151 | 1999 |
| Efficient hardware architectures for deep convolutional neural network J Wang, J Lin, Z Wang IEEE Transactions on Circuits and Systems I: Regular Papers 65 (6), 1941-1953, 2017 | 142 | 2017 |
| Error correction for multi-level NAND flash memory using Reed-Solomon codes B Chen, X Zhang, Z Wang 2008 IEEE Workshop on Signal Processing Systems, 94-99, 2008 | 132 | 2008 |
| Design of sequential elements for low power clocking system P Zhao, J McNeely, W Kuang, N Wang, Z Wang IEEE Transactions on very large scale integration (VLSI) systems 19 (5), 914-918, 2010 | 114 | 2010 |
| Area-efficient high-speed decoding schemes for turbo decoders Z Wang, Z Chi, KK Parhi IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10 (6), 902-912, 2002 | 108 | 2002 |
| Accelerating recurrent neural networks: A memory-efficient approach Z Wang, J Lin, Z Wang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (10 …, 2017 | 91 | 2017 |
| Efficient decoder design for nonbinary quasicyclic LDPC codes J Lin, J Sha, Z Wang, L Li IEEE Transactions on Circuits and Systems I: Regular Papers 57 (5), 1071-1082, 2010 | 86 | 2010 |
| High-speed low-power Viterbi decoder design for TCM decoders J He, H Liu, Z Wang, X Huang, K Zhang IEEE transactions on very large scale integration (vlsi) systems 20 (4), 755-759, 2011 | 79 | 2011 |
| TIE: Energy-efficient tensor train-based inference engine for deep neural network C Deng, F Sun, X Qian, J Lin, Z Wang, B Yuan Proceedings of the 46th International Symposium on Computer Architecture …, 2019 | 77 | 2019 |
| An energy-efficient architecture for binary weight convolutional neural networks Y Wang, J Lin, Z Wang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (2), 280-293, 2017 | 77 | 2017 |
| High-throughput layered LDPC decoding architecture Z Cui, Z Wang, Y Liu IEEE transactions on very large scale integration (VLSI) systems 17 (4), 582-587, 2009 | 77 | 2009 |
| Improved K-best sphere decoding algorithms for MIMO systems Q Li, Z Wang 2006 IEEE International Symposium on Circuits and Systems (ISCAS), 4 pp.-1162, 2006 | 77 | 2006 |
| Hardware accelerator for multi-head attention and position-wise feed-forward in the transformer S Lu, M Wang, S Liang, J Lin, Z Wang 2020 IEEE 33rd International System-on-Chip Conference (SOCC), 84-89, 2020 | 75 | 2020 |
| Flexible LDPC decoder design for multigigabit-per-second applications C Zhang, Z Wang, J Sha, L Li, J Lin IEEE Transactions on Circuits and Systems I: Regular Papers 57 (1), 116-124, 2009 | 72 | 2009 |
| A memory efficient partially parallel decoder architecture for quasi-cyclic LDPC codes Z Wang, Z Cui IEEE transactions on very large scale integration (VLSI) systems 15 (4), 483-488, 2007 | 72 | 2007 |
| Efficient precision-adjustable architecture for softmax function in deep learning D Zhu, S Lu, M Wang, J Lin, Z Wang IEEE Transactions on Circuits and Systems II: Express Briefs 67 (12), 3382-3386, 2020 | 66 | 2020 |
