| Efficient design-for-test approach for networks-on-chip J Wang, M Ebrahimi, L Huang, X Xie, Q Li, G Li, A Jantsch IEEE Transactions on Computers 68 (2), 198-213, 2018 | 28 | 2018 |
| Non-blocking testing for network-on-chip L Huang, J Wang, M Ebrahimi, M Daneshtalab, X Zhang, G Li, A Jantsch IEEE Transactions on Computers 65 (3), 679-692, 2015 | 21 | 2015 |
| Design of Fault-Tolerant and Reliable Networks-on-Chip GL Junshi Wang, Masoumeh Ebrahimi, Letian Huang, Axel Jantsch IEEE Computer Society Annual Symposium on VLSI, 1-6, 2015 | 16* | 2015 |
| VisualNoC: A Visualization and Evaluation Environment for Simulation and Mapping GL Junshi Wang, Yang Huang, Masoumeh Ebrahimi, Letian Huang, Qiang Li, Axel ... Third ACM International Workshop on Many-core Embedded Systems, 2016 | 13 | 2016 |
| Wena: Deterministic run-time task mapping for performance improvement in many-core embedded systems LT Huang, H Dong, JS Wang, M Daneshtalab, GJ Li IEEE Embedded Systems Letters 7 (4), 93-96, 2015 | 13 | 2015 |
| A lifetime-aware mapping algorithm to extend MTTF of networks-on-chip L Huang, S Chen, Q Wu, M Ebrahimi, J Wang, S Jiang, Q Li 2018 23rd Asia and South Pacific design automation conference (ASP-DAC), 147-152, 2018 | 10 | 2018 |
| A fault-tolerant routing algorithm for NoC using farthest reachable routers J Wang, X Wang, L Huang, T Mak, G Li 2013 IEEE 11th International Conference on Dependable, Autonomic and Secure …, 2013 | 8 | 2013 |
| Rescuing healthy cores against disabled routers M Ebrahimi, J Wang, L Huang, M Daneshtalab, A Jantsch 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2014 | 7 | 2014 |
| Optimizing dynamic mapping techniques for on-line NoC test S Jiang, Q Wu, S Chen, J Wang, M Ebrahimi, L Huang, Q Li 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 227-232, 2018 | 6 | 2018 |
| Optimizing the location of ECC protection in network-on-chip AJ Junshi Wang, Letian Huang, Qiang Li, Guangjun Li Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on …, 2016 | 5* | 2016 |
| Micro-architecture design for low overhead fault tolerant network-on-chip C Yuan, L Huang, J Wang, Q Li 2018 IEEE international symposium on circuits and systems (ISCAS), 1-5, 2018 | 4 | 2018 |
| Testing aware dynamic mapping for path-centric network-on-chip test S Jiang, Q Wu, S Chen, J Zhan, J Wang, M Ebrahimi, L Huang Integration 67, 134-143, 2019 | 3 | 2019 |
| Optimized mapping algorithm to extend lifetime of both NoC and cores in many-core system L Wang, S Jiang, S Chen, J Wang, L Huang Integration 67, 82-94, 2019 | 2 | 2019 |
| Review on Fault-Tolerant NoC Designs JS Wang, LT Huang Journal of Electronic Science and Technology 16 (3), 193-223, 2018 | 2 | 2018 |
| A low latency fault tolerant transmission mechanism for Network-on-Chip L Huang, X Lin, J Wang, Q Li 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 2 | 2017 |
| Estimating power for FPGAs based on signal probability theory JS Wang, LT Huang, H Dong, T Mak Journal of Electronic Science and Technology 10 (4), 302-308, 2012 | 2 | 2012 |
| Non-blocking BIST for continuous reliability monitoring of Networks-on-Chip J Wang, L Huang, M Ebrahimi, Q Li, G Li, A Jantsch 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 1 | 2017 |
| Visualnoc: Visualization network-on-chipp design framework J Wang, L Huang, G Li, A Jantsch Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016 | 1 | 2016 |
| Minimizing the System Impact of Router Faults by Means of Reconfiguration and Adaptive Routing AJ Junshi Wang, Masoumeh Ebrahimi, Letian Huang, Qiang Li, Guangjun Li Microprocessors and Microsystems, 2017 | | 2017 |
| Calculation of delivery rate in fault‐tolerant network‐on‐chips J Wang, L Huang, G Li, A Jantsch Electronics Letters 52 (7), 546-548, 2016 | | 2016 |
letian huang电子科技大学在 uestc.edu.cn 的电子邮件经过验证
