| Exploring Instruction Fusion Opportunities in General Purpose Processors S Singh, A Perais, A Jimborean, A Ros In Proceedings of the 55th International Symposium on Microarchitecture, 2022 | 4 | 2022 |
| Regional out-of-order writes in total store order S Singh, A Jimborean, A Ros Proceedings of the ACM International Conference on Parallel Architectures …, 2020 | 3 | 2020 |
| Microarchitectural Optimizations for an Efficient Utilization of Processor Resources S Singh Proyecto de investigación:, 2024 | | 2024 |
| Alternate Path μ-op Cache Prefetching S Singh, A Perais, A Jimborean, A Ros 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture …, 2024 | | 2024 |
| CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions S Singh, J Feliu, ME Acacio, A Jimborean, A Ros Proceedings of the International Conference on Parallel Architectures and …, 2023 | | 2023 |
| Dual Consistency Store Buffer for Out Of Order Processors S SAWAN, A ROS, G MASERA | | 2019 |
| HDL Code Generation Of Efficient DCT Architecture Using MATLAB HDL Coder S Singh International Journal of Innovative Research in Computer and Communication …, 2016 | | 2016 |
| Generation Of HDL Codes Of Different Image Processing Algorithms And Efficient DCT Architecture Using MATLAB HDL Coder S Singh | | 2016 |
Alberto RosUniversity of Murcia在 ditec.um.es 的电子邮件经过验证
