| KernelFaRer: replacing native-code idioms with high-performance library calls JPL De Carvalho, B Kuzma, I Korostelev, JN Amaral, C Barton, J Moreira, ... ACM Transactions On Architecture And Code Optimization (TACO) 18 (3), 1-22, 2021 | 21 | 2021 |
| Energy-performance tradeoffs in software transactional memory A Baldassin, JPL De Carvalho, LAG Garcia, R Azevedo 2012 IEEE 24th International Symposium on Computer Architecture and High …, 2012 | 20 | 2012 |
| The case for phase-based transactional memory JPL de Carvalho, G Araujo, A Baldassin IEEE Transactions on Parallel and Distributed Systems 30 (2), 459-472, 2018 | 11 | 2018 |
| Revisiting phased transactional memory JPL De Carvalho, G Araujo, A Baldassin Proceedings of the International Conference on Supercomputing, 1-10, 2017 | 8 | 2017 |
| To pack or not to pack: A generalized packing analysis and transformation C Salvador Rohwedder, N Henderson, JPL De Carvalho, Y Chen, ... Proceedings of the 21st ACM/IEEE International Symposium on Code Generation …, 2023 | 7 | 2023 |
| Pooling acceleration in the DaVinci architecture using Im2col and Col2im instructions CS Rohwedder, JPL de Carvalho, JN Amaral, G Araújo, G Colmenares, ... 2021 IEEE International Parallel and Distributed Processing Symposium …, 2021 | 6 | 2021 |
| On the Efficiency of Transactional Code Generation: A GCC Case Study BC Honorio, JPL Carvalho, A Baldassin Simpósio de Sistemas Computacionais de Alto Desempenho (WSCAD), 2018 | 6 | 2018 |
| NV-PhTM: An Efficient Phase-Based Transactional System for Non-Volatile Memory A Baldassin, RP Murari, JPL Carvalho, G Araujo, D Castro, J Barreto, ... Euro-Par: 26th International European Conference on Parallel and Distributed …, 2020 | 5 | 2020 |
| An Efficient Parallel Implementation for Training Supervised Optimum-Path Forest Classifiers A Culquicondor, A Baldassin, C Castelo-Fernandéz, JPL Carvalho, ... Neurocomputing, 2018 | 5 | 2018 |
| Advancing direct convolution using convolution slicing optimization and ISA extensions V Ferrari, R Sousa, M Pereira, JP L. De Carvalho, JN Amaral, J Moreira, ... ACM Transactions on Architecture and Code Optimization 20 (4), 1-26, 2023 | 4 | 2023 |
| Compiling for the IBM Matrix Engine for Enterprise Workloads JPL de Carvalho, JE Moreira, JN Amaral IEEE MICRO, 1-8, 2022 | 4 | 2022 |
| Reavaliando a Eficiência Energética de Memória Transacional em Processadores Convencionais JPL de Carvalho, A Baldassin, R Azevedo Simpósio em Sistemas Computacionais de Alto Desempenho (SSCAD), 69-76, 2013 | 4 | 2013 |
| YaConv: Convolution with low cache footprint I Korostelev, JP L. De Carvalho, J Moreira, JN Amaral ACM Transactions on Architecture and Code Optimization 20 (1), 1-18, 2023 | 3 | 2023 |
| Improving transactional code generation via variable annotation and barrier elision JPL De Carvalho, BC Honorio, A Baldassin, G Araujo 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2020 | 3 | 2020 |
| Fast matrix multiplication via compiler‐only layered data reorganization and intrinsic lowering B Kuzma, I Korostelev, JPL de Carvalho, JE Moreira, C Barton, G Araujo, ... Software: Practice and Experience 53 (9), 1793-1814, 2023 | 2 | 2023 |
| Vectorizing divergent control fow with active‑lane consolidation on long‑vector architectures W Praharenka, D Pankratz, JPL de Carvalho, E Amiri, JN Amaral The Journal of Supercomputing, 2022 | 2 | 2022 |
| Acceleration opportunities in linear algebra applications via idiom recognition JP L. de Carvalho, B Kuzma, G Araujo Companion of the ACM/SPEC International Conference on Performance …, 2020 | 2 | 2020 |
| DOACROSS Parallelization Based on Component Annotation and Loop-carried Probability L Mattos, D Cesar, J Salamanca, JPL de Carvalho, M Pereira, G Araujo 30th International Symposium on Computer Architecture and High Performance …, 2018 | 2 | 2018 |
| Reavaliando o conjunto de aplicacoes stamp em um novo hardware transacional JP de Carvalho, R Murari, A Baldassin Simpósio em Sistemas Computacionais de Alto Desempenho (SSCAD), 216-227, 2015 | 2 | 2015 |
| Improving convolution via cache hierarchy tiling and reduced packing V Ferrari, R Sousa, M Pereira, JPL de Carvalho, JN Amaral, G Araujo Proceedings of the International Conference on Parallel Architectures and …, 2022 | 1 | 2022 |
Guido AraujoIC-UNICAMP在 ic.unicamp.br 的电子邮件经过验证
