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Hao Zheng
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An energy-efficient network-on-chip design using reinforcement learning
H Zheng, A Louri
Proceedings of ACM/IEEE Design Automation Conference (DAC), 1-6, 2019
612019
Adapt-noc: A flexible network-on-chip design for heterogeneous manycore architectures
H Zheng, K Wang, A Louri
Proceedings of IEEE International Symposium on High-performance Computer …, 2021
422021
A versatile and flexible chiplet-based system design for heterogeneous manycore architectures
H Zheng, K Wang, A Louri
Proceedings of ACM/IEEE Design Automation Conference (DAC), 1-6, 2020
352020
Ez-pass: An energy & performance-efficient power-gating router architecture for scalable nocs
H Zheng, A Louri
IEEE Computer Architecture Letters 17 (1), 88-91, 2018
312018
TSA-NoC: Learning-Based Threat Detection and Mitigation for Secure Network-on-Chip Architecture
K Wang, H Zheng, A Louri
IEEE Micro 40 (5), 56-63, 2020
272020
Agile: A learning-enabled power and performance-efficient network-on-chip design
H Zheng, A Louri
IEEE Transactions on Emerging Topics in Computing 10 (1), 223-236, 2020
242020
SGCNAX: A scalable graph convolutional neural network accelerator with workload balancing
J Li, H Zheng, K Wang, A Louri
IEEE Transactions on Parallel and Distributed Systems (TPDS) 33 (11), 2834-2845, 2021
182021
Ascend: A scalable and energy-efficient deep neural network accelerator with photonic interconnects
Y Li, K Wang, H Zheng, A Louri, A Karanth
IEEE Transactions on Circuits and Systems I: Regular Papers 69 (7), 2730-2741, 2022
172022
Adapt-Flow: A Flexible DNN Accelerator Architecture for Heterogeneous Dataflow Implementation
J Yang, H Zheng, A Louri
Proceedings of the Great Lakes Symposium on VLSI (GLSVLIS), 287-292, 2022
122022
Venus: A versatile deep neural network accel-erator architecture design for multiple applications
J Yang, H Zheng, A Louri
Proceedings of ACM/IEEE Design Automation Conference (DAC), 2023
82023
Exploring architecture, dataflow, and sparsity for gcn accelerators: A holistic framework
L Yin, J Wang, H Zheng
Proceedings of the Great Lakes Symposium on VLSI (GLSVLIS), 489-495, 2023
72023
AGAPE: anomaly detection with generative adversarial network for improved performance, energy, and security in manycore systems
K Wang, H Zheng, Y Li, J Li, A Louri
Proceedings of Design, Automation & Test in Europe Conference & Exhibition …, 2022
62022
SecureNoC: A learning-enabled, high-performance, energy-efficient, and secure on-chip communication framework design
K Wang, H Zheng, Y Li, A Louri
IEEE Transactions on Sustainable Computing 7 (3), 709-723, 2021
62021
Aries: Accelerating distributed training in chiplet-based systems via flexible interconnects
L Yin, A Ghazizadeh, A Louri, H Zheng
Proceedings of IEEE/ACM International Conference on Computer Aided Design …, 2023
32023
GShuttle: Optimizing Memory Access Efficiency for Graph Convolutional Neural Network Accelerators
JJ Li, K Wang, H Zheng, A Louri
Journal of computer science and technology 38 (1), 115-127, 2023
32023
Interconnection network with adaptable router lines for chiplet-based manycore architecture
H Zheng, K Wang, A Louri
US Patent 11,489,788, 2022
32022
SAGA: Sparsity-Agnostic Graph Convolutional Network Acceleration with Near-Optimal Workload Balance
S Gandham, L Yin, H Zheng, M Lin
Proceedings of IEEE/ACM International Conference on Computer Aided Design …, 2023
22023
FDMAX: An Elastic Accelerator Architecture for Solving Partial Differential Equations
J Li, Y Zhang, H Zheng, K Wang
Proceedings of ACM/IEEE International Symposium on Computer Architecture …, 2023
22023
Systems and methods for learning-based high-performance, energy-efficient, and secure on-chip communication design framework
K Wang, H Zheng, A Louri
US Patent App. 17/307,563, 2021
22021
Versa-DNN: A Versatile Architecture Enabling High-Performance and Energy-Efficient Multi-DNN Acceleration
J Yang, H Zheng, A Louri
IEEE Transactions on Parallel and Distributed Systems (TPDS), 2024
12024
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