| Stack chip and stack chip package having the same JJ Lee, DH Lee US Patent 7,768,115, 2010 | 257 | 2010 |
| Three-dimensional stacked structure semiconductor device having through-silicon via and signaling method for the semiconductor device JJ Lee US Patent 8,471,362, 2013 | 104 | 2013 |
| Semiconductor device package having buffered memory module and method thereof JJ Lee, Y Song US Patent 7,821,127, 2010 | 81 | 2010 |
| Area array type package stack and manufacturing method thereof JJ Lee US Patent App. 10/798,943, 2005 | 81 | 2005 |
| Planar multi semiconductor chip package and method of manufacturing the same JJ Lee US Patent 7,675,181, 2010 | 57 | 2010 |
| Stack package SD Baek, SW Kang, JJ Lee US Patent 8,097,940, 2012 | 51 | 2012 |
| Multi-chip ball grid array package JJ Lee, DH Lee US Patent 7,064,444, 2006 | 42 | 2006 |
| Suppression of coupled-slotline mode on CPW using air-bridges measured by picosecond photoconductive sampling J Lee, H Lee, W Kim, J Lee, J Kim IEEE microwave and guided wave letters 9 (7), 265-267, 1999 | 41 | 1999 |
| Chip stack, chip stack package, and method of forming chip stack and chip stack package JJ Lee, SW Kang US Patent 7,964,948, 2011 | 37 | 2011 |
| Semiconductor package having heat spreader and package stack using the same JJ Lee, Y Song US Patent 7,317,247, 2008 | 37 | 2008 |
| Multi-chip package and method of manufacturing the same UB Kang, JJ Lee, YH Kim, TH Min US Patent 8,633,579, 2014 | 24 | 2014 |
| Near-field probe for use in scanning system J Lee, J Kim US Patent 6,873,165, 2005 | 24 | 2005 |
| Closed-form expressions for the noise voltage caused by a burst train of IC switching currents on a power distribution network J Kim, J Lee, S Ahn, J Fan IEEE Transactions on Electromagnetic Compatibility 56 (6), 1585-1597, 2014 | 23 | 2014 |
| Stack chip and stack chip package having the same JJ Lee, DH Lee US Patent 7,462,930, 2008 | 23 | 2008 |
| Semiconductor device having a conductive bump DK Shin, SG Lee, JJ Lee, J Lee US Patent 8,120,176, 2012 | 20 | 2012 |
| Chip stack, method of fabrication thereof, and semiconductor package having the same JJ Lee US Patent App. 11/710,490, 2007 | 20 | 2007 |
| Semiconductor package including redistribution pattern and method of manufacturing the same SD Baek, DH Jang, JJ Lee US Patent 7,274,097, 2007 | 19 | 2007 |
| Chip stack package SW Kang, SD Baek, JJ Lee US Patent 8,039,928, 2011 | 18 | 2011 |
| An enhanced statistical analysis method for I/O links considering supply voltage fluctuations and intersymbol interference J Kim, J Lee, E Park, Y Park IEEE Transactions on Components, Packaging and Manufacturing Technology 5 (8 …, 2015 | 17 | 2015 |
| Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the same JJ Lee US Patent 7,545,037, 2009 | 17 | 2009 |
Jingook KimProfessor, Ulsan National Institute of Science and Technology在 unist.ac.kr 的电子邮件经过验证
