| Improved design debugging using maximum satisfiability S Safarpour, H Mangassarian, A Veneris, MH Liffiton, KA Sakallah Formal Methods in Computer Aided Design (FMCAD'07), 13-19, 2007 | 154 | 2007 |
| QBF-based formal verification: Experience and perspectives M Benedetti, H Mangassarian Journal on Satisfiability, Boolean Modeling and Computation 5 (1-4), 133-191, 2009 | 100 | 2009 |
| A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test H Mangassarian, A Veneris, S Safarpour, M Benedetti, D Smith 2007 IEEE/ACM International Conference on Computer-Aided Design, 240-245, 2007 | 60 | 2007 |
| Robust QBF encodings for sequential circuits with applications to verification, debug, and test H Mangassarian, A Veneris, M Benedetti IEEE Transactions on Computers 59 (7), 981-994, 2010 | 45 | 2010 |
| Maximum circuit activity estimation using pseudo-boolean satisfiability H Mangassarian, A Veneris, S Safarpour, FN Najm, MS Abadir 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 28 | 2007 |
| On statistical timing analysis with inter-and intra-die variations H Mangassarian, M Anis Design, Automation and Test in Europe, 132-137, 2005 | 28 | 2005 |
| Trace compaction using SAT-based reachability analysis S Safarpour, A Veneris, H Mangassarian 2007 Asia and South Pacific Design Automation Conference, 932-937, 2007 | 19 | 2007 |
| Maximum circuit activity estimation using pseudo-boolean satisfiability H Mangassarian, A Veneris, FN Najm IEEE Transactions on computer-aided design of integrated circuits and …, 2012 | 18 | 2012 |
| Method, system and computer program for automated hardware design debugging A Veneris, S Safarpour, MYF Ali, H Mangassarian US Patent App. 11/556,466, 2008 | 18 | 2008 |
| Non-solution implications using reverse domination in a modern SAT-based debugging environment B Le, H Mangassarian, B Keng, A Veneris 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 629-634, 2012 | 13 | 2012 |
| On error tolerance and engineering change with partially programmable circuits H Mangassarian, H Yoshida, A Veneris, S Yamashita, M Fujita 17th Asia and South Pacific Design Automation Conference, 695-700, 2012 | 12 | 2012 |
| Debugging RTL using structural dominance H Mangassarian, B Le, A Veneris IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 10 | 2013 |
| Debugging with dominance: On-the-fly RTL debug solution implications H Mangassarian, A Veneris, DE Smith, S Safarpour 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 587-594, 2011 | 9 | 2011 |
| Fault diagnosis using quantified boolean formulas H Mangassarian, A Veneris, M Benedetti Proceedings of the 4th IEEE Silicon Debug and Diagnosis Workshop, Freiburg …, 2007 | 7 | 2007 |
| Leveraging dominators for preprocessing QBF H Mangassarian, B Le, A Goultiaeva, A Veneris, F Bacchus 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 5 | 2010 |
| A succinct memory model for automated design debugging B Keng, H Mangassarian, A Veneris 2008 IEEE/ACM International Conference on Computer-Aided Design, 137-142, 2008 | 5 | 2008 |
| Formal methods in computer-aided design H Mangassarian University of Toronto (Canada), 2012 | 2 | 2012 |
| Software solutions to automating data analysis and acquisition setup in silicon debug YS Yang, B Keng, A Veneris, N Nicolici, H Mangassarian Proc. IEEE SDD Workshop, 2010 | 1 | 2010 |
| A Performance-Driven QBF-Based ILA Representation with Applications to Verification, Debug and Test H Mangassarian, A Veneris, S Safarpour, M Benedetti, D Smith International Conference on Computer-aided Design (ICCAD), 1-6, 2007 | 1 | 2007 |
| Pseudo-Boolean satisfiability and quantified Boolean formulas in CAD for VLSI H Mangassarian | | 2008 |
