| Implementation of smart home through fpga using verilog hardware descriptive language R Payal, A Saxena, B Chanda 2020 IEEE International Conference on Advent Trends in Multidisciplinary …, 2020 | 10 | 2020 |
| Design and implementation of parallel prefix adder for improving the performance of carry lookahead adder R Payal, M Goel, P Manglik International Journal of Engineering Research & Technology 4 (12), 566-571, 2015 | 9 | 2015 |
| A Study on different hardware and cloud based internet of things platforms R Payal, AP Singh Journal of Physics: Conference Series 1916 (1), 012055, 2021 | 4 | 2021 |
| A study of various hardware and cloud based Internet of Things platforms R Payal, AP Singh R. EasyChair, 2020 | 2 | 2020 |
| Simulation and Synthesis Model for the Addition of Single Precision Floating Point Numbers Using VERILOG R Payal International Journal of Engineering Research & Technology (IJERT) 2 (9), 2013 | 2 | 2013 |
| Analysis of Kogge-Stone and ladner fischer parallel prefix adder using verilog HDL R Payal, AP Singh AIP Conference Proceedings 3059 (1), 2024 | 1 | 2024 |
| Synthesis of KNN Algorithm in FPGA Technology R Payal, AP Singh Advances in Micro-Electronics, Embedded Systems and IoT: Proceedings of …, 2022 | 1 | 2022 |
| Model for home automation system through FPGA R Payal, AP Singh Recent Advances in Computing Sciences, 96-103, 2023 | | 2023 |
| Design of a multi-functional communication interface for Low power applications R Payal 2021 12th International Conference on Computing Communication and Networking …, 2021 | | 2021 |
| INTERNET OF THINGS (IoT) FOR SMART CITIES R PAYAL, AP SINGH | | 2021 |
| Simulation Model Of Wallace Tree Multiplier Using Verilog R Payal | | |
| International Journal Of Scientific Research And Education R Payal, U Kapoor, H Chugh | | |
