| Design solutions for sample-and-hold circuits in CMOS nanometer technologies F Centurelli, P Monsurro, S Pennisi, G Scotti, A Trifiletti IEEE Transactions on Circuits and Systems II: Express Briefs 56 (6), 459-463, 2009 | 60 | 2009 |
| Efficient digital background calibration of time-interleaved pipeline analog-to-digital converters F Centurelli, P Monsurro, A Trifiletti IEEE Transactions on Circuits and Systems I: Regular Papers 59 (7), 1373-1383, 2012 | 54 | 2012 |
| Linearization technique for source-degenerated CMOS differential transconductors P Monsurro, S Pennisi, G Scotti, A Trifiletti IEEE Transactions on Circuits and Systems II: Express Briefs 54 (10), 848-852, 2007 | 53 | 2007 |
| 88-A 1-MHz Stray-Insensitive CMOS Current-Mode Interface IC for Differential Capacitive Sensors G Scotti, S Pennisi, P Monsurrò, A Trifiletti IEEE Transactions on Circuits and Systems I: Regular Papers 61 (7), 1905-1916, 2014 | 47 | 2014 |
| Exploiting the body of MOS devices for high performance analog design P Monsurro, S Pennisi, G Scotti, A Trifiletti IEEE Circuits and Systems Magazine 11 (4), 8-23, 2011 | 42 | 2011 |
| 0.9‐V CMOS cascode amplifier with body‐driven gain boosting P Monsurro, S Pennisi, G Scotti, A Trifiletti International Journal of Circuit Theory and Applications 37 (2), 193-202, 2009 | 41 | 2009 |
| Behavioral modeling for calibration of pipeline analog-to-digital converters F Centurelli, P Monsurro, A Trifiletti IEEE Transactions on Circuits and Systems I: Regular Papers 57 (6), 1255-1264, 2010 | 39 | 2010 |
| Secure double rate registers as an RTL countermeasure against power analysis attacks D Bellizia, S Bongiovanni, P Monsurrò, G Scotti, A Trifiletti, FB Trotta IEEE transactions on very large scale integration (vlsi) systems 26 (7 …, 2018 | 37 | 2018 |
| Biasing technique via bulk terminal for minimum supply CMOS amplifiers P Monsurrò, G Scotti, A Trifiletti, S Pennisi Electronics Letters 41 (14), 1, 2005 | 37 | 2005 |
| A topology of fully differential class-AB symmetrical OTA with improved CMRR F Centurelli, P Monsurrò, G Parisi, P Tommasino, A Trifiletti IEEE Transactions on Circuits and Systems II: Express Briefs 65 (11), 1504-1508, 2017 | 34 | 2017 |
| Analysis and implementation of a minimum-supply body-biased CMOS differential amplifier cell AD Grasso, P Monsurro, S Pennisi, G Scotti, A Trifiletti IEEE transactions on very large scale integration (VLSI) systems 17 (2), 172-180, 2008 | 34 | 2008 |
| Univariate power analysis attacks exploiting static dissipation of nanometer CMOS VLSI circuits for cryptographic applications D Bellizia, S Bongiovanni, P Monsurrò, G Scotti, A Trifiletti IEEE Transactions on Emerging Topics in Computing 5 (3), 329-339, 2016 | 32 | 2016 |
| Low power DDA-based instrumentation amplifier for neural recording applications in 65 nm CMOS M Avoli, F Centurelli, P Monsurrò, G Scotti, A Trifiletti AEU-International Journal of Electronics and Communications 92, 30-35, 2018 | 30 | 2018 |
| A class-AB flipped voltage follower output stage F Centurelli, P Monsurrò, A Trifiletti 2011 20th European Conference on Circuit Theory and Design (ECCTD), 757-760, 2011 | 30 | 2011 |
| New models for the calibration of four-channel time-interleaved ADCs using filter banks P Monsurrò, F Rosato, A Trifiletti IEEE Transactions on Circuits and Systems II: Express Briefs 65 (2), 141-145, 2017 | 27 | 2017 |
| Improved digital background calibration of time-interleaved pipeline A/D converters F Centurelli, P Monsurro, A Trifiletti IEEE Transactions on Circuits and Systems II: Express Briefs 60 (2), 86-90, 2013 | 27 | 2013 |
| A 0.3 V rail-to-rail ultra-low-power OTA with improved bandwidth and slew rate F Centurelli, R Della Sala, P Monsurrò, G Scotti, A Trifiletti Journal of Low Power Electronics and Applications 11 (2), 19, 2021 | 26 | 2021 |
| 0.6‐V CMOS cascode OTA with complementary gate‐driven gain‐boosting and forward body bias D Cellucci, F Centurelli, V Di Stefano, P Monsurrò, S Pennisi, G Scotti, ... International Journal of Circuit Theory and Applications 48 (1), 15-27, 2020 | 26 | 2020 |
| Calibration of time-interleaved ADCs via Hermitianity-preserving Taylor approximations P Monsurrò, A Trifiletti IEEE Transactions on Circuits and Systems II: Express Briefs 64 (4), 357-361, 2016 | 24 | 2016 |
| Streamline calibration modelling for a comprehensive design of ATI-based digitizers P Monsurrò, A Trifiletti, L Angrisani, M D'Arco Measurement 125, 386-393, 2018 | 22 | 2018 |
