| SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems M Fakih, A Lenz, M Azkarate-Askasua, J Coronel, A Crespo, ... Microprocessors and Microsystems 52, 89-105, 2017 | 25 | 2017 |
| Adaptive Time-Triggered Multi-Core Architecture R Obermaisser, H Ahmadian, A Maleki, Y Bebawy, A Lenz, B Sorkhpour Designs 3 (1), 7, 2019 | 20 | 2019 |
| Global Adaptation for Energy Efficiency in Multicore Architectures A Lenz, T Pieper, R Obermaisser Parallel, Distributed and Network-based Processing (PDP), 2017 25th …, 2017 | 10 | 2017 |
| SAFEPOWER Project: Architecture for Safe and Power-Efficient Mixed-Criticality Systems A Lenz, MAA Blázquez, J Coronel, A Crespo, S Davidmann, JCD Garcia, ... Digital System Design (DSD), 2016 Euromicro Conference on, 294-300, 2016 | 10 | 2016 |
| Global Adaptation Controlled by an Interactive Consistency Protocol A Lenz, R Obermaisser Journal of Low Power Electronics and Applications 7 (2), 13, 2017 | 8 | 2017 |
| Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems M Fakih, K Grüttner, S Schreiner, R Seyyedi, M Azkarate-Askasua, ... Journal of Low Power Electronics and Applications 9 (1), 12, 2019 | 7 | 2019 |
| System-wide, fault-tolerant state agreement protocol for time-triggered MPSoC A Lenz | | 2020 |
| Adaptive Time-Triggered Multi-Core Architecture H Ahmadian, A Maleki, Y Bebawy, A Lenz, B Sorkhpour Designs 3 (1), 7, 2019 | | 2019 |
