| A 1.3–4-GHz quadrature-phase digital DLL using sequential delay control and reconfigurable delay line H Park, J Sim, Y Choi, J Choi, Y Kwon, S Park, G Park, J Chung, KM Kim, ... IEEE Journal of Solid-State Circuits 56 (6), 1886-1896, 2021 | 13 | 2021 |
| A 33-Gb/s/Pin 1.09-pJ/bit single-ended PAM-3 transceiver with ground-referenced signaling and time-domain decision technique for multi-chip module memory interfaces Y Kwon, H Park, Y Choi, J Sim, J Choi, S Park, KM Kim, C Choi, HK Jung, ... IEEE Journal of Solid-State Circuits 58 (8), 2314-2325, 2023 | 9 | 2023 |
| A 0.83 pJ/b 52Gb/s PAM-4 baud-rate CDR with pattern-based phase detector for short-reach applications S Park, Y Choi, J Sim, J Choi, H Park, Y Kwon, C Kim 2023 IEEE International Solid-State Circuits Conference (ISSCC), 118-120, 2023 | 9 | 2023 |
| A 15 Gb/s non-return-to-zero transmitter with 1-tap pre-emphasis feed-forward equalizer for low-power ground terminated memory interfaces Y Kwon, H Park, Y Choi, J Sim, J Choi, S Park, C Kim IEEE Transactions on Circuits and Systems II: Express Briefs 69 (6), 2737-2741, 2022 | 8 | 2022 |
| Analysis of a multiwire, multilevel, and symbol correlation combination scheme J Choi, Y Choi, H Park, J Sim, Y Kwon, S Park, C Kim IEEE Transactions on Circuits and Systems I: Regular Papers 69 (8), 3416-3427, 2022 | 4 | 2022 |
| A Four-Phase Time-Based Switched-Capacitor LDO With 13-ns Settling Time at 0.5-V Input for Energy-Efficient Computing in SoC Applications H Kim, C Park, I Park, T Park, S Park, C Kim IEEE Journal of Solid-State Circuits, 2023 | 3 | 2023 |
| A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces Y Choi, H Park, J Choi, J Sim, Y Kwon, S Park, S Kim, C Sim, C Kim IEEE Journal of Solid-State Circuits 58 (7), 2005-2015, 2022 | 3 | 2022 |
| Single-Ended PAM-4 Transmitters With Data Bus Inversion and ZQ Calibration for High-Speed Memory Interfaces S Kim, J Sim, Y Choi, J Choi, Y Kwon, S Park, C Sim, J So, T Park, C Kim IEEE Journal of Solid-State Circuits, 2024 | 1 | 2024 |
| A 0.458-pJ/bit 24-Gb/s/pin Capacitively Driven PAM-4 Transceiver With PAM-Based Crosstalk Cancellation for High-Density Die-to-Die Interfaces S Kim, C Sim, J Sim, J Choi, Y Kwon, S Park, J So, H Shin, SB Lee, C Kim IEEE Journal of Solid-State Circuits, 2024 | 1 | 2024 |
| A 4-GHz Ring-Oscillator-Based Digital Sub-Sampling PLL With Energy-Efficient Dual-Domain Phase Detector Y Choi, H Park, J Choi, J Sim, Y Kwon, S Park, C Sim, C Kim IEEE Transactions on Circuits and Systems I: Regular Papers 70 (7), 2734-2743, 2023 | 1 | 2023 |
| A 16-Gb/s NRZ Receiver With 0.0019-pJ/bit/dB 1-Tap Charge-Redistribution DFE J Choi, Y Choi, H Park, J Sim, Y Kwon, S Park, S Kim, C Kim IEEE Transactions on Circuits and Systems II: Express Briefs 70 (3), 904-908, 2022 | 1 | 2022 |
| A 25-Gb/s Single-Ended PAM-4 Transmitter With iPWM-Based FFE and RLM-Matched Voltage-Mode Driver for High-Speed Memory Interfaces Y Choi, C Sim, J Choi, J Sim, H Park, Y Kwon, S Park, S Kim, C Kim IEEE Transactions on Circuits and Systems I: Regular Papers, 2024 | | 2024 |
| A 0.45 pJ/b 24 Gb/s NRZ Receiver Data-Path Using Half-Baud-Rate Duobinary Sampling S Park, Y Choi, J Choi, J Sim, Y Kwon, C Sim, S Kim, C Kim IEEE Transactions on Circuits and Systems II: Express Briefs, 2024 | | 2024 |
| A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces J Choi, Y Choi, J Sim, Y Kwon, S Park, S Kim, C Sim, C Kim IEEE Journal of Solid-State Circuits, 2024 | | 2024 |
| A Wireline Transceiver With 3-bit per Symbol Using Common-Mode NRZ and Differential-Mode PAM-4 Signaling Techniques J Sim, J Choi, Y Kwon, S Park, S Kim, C Sim, H Shin, J So, S Lee, C Kim IEEE Journal of Solid-State Circuits, 2024 | | 2024 |
| A 13-Gb/s Single-Ended NRZ Receiver With 1-Sample per 2-UI Using Data Edge Sampling for Memory Interfaces H Kang, Y Choi, J Sim, J Choi, Y Kwon, S Park, S Kim, C Sim, C Kim IEEE Transactions on Circuits and Systems II: Express Briefs, 2024 | | 2024 |
| A 10-Gb/s Wireline Receiver Using Linear Baud-Rate CDR and Analog Equalizer for Free Space Optical Communication Over 10-and 100-m Distances J Sim, C Sim, H Park, Y Choi, J Choi, Y Kwon, S Park, S Kim, JM Kim, ... IEEE Journal of Solid-State Circuits, 2024 | | 2024 |
| A SINGLE-ENDED RECEIVER CIRCUIT USING TRUE-SINGLE-PHASE HALF RATE CLOCK C Kim, HS Kang, J Sim, Y Kwon, S Kim, S Park KR Patent App., 0 | | |
| Clock Data Recovery Device and Operation Method for Receiver of Wireless Optical Communication C Kim, J Sim, Y Kwon, S Kim, S Park KR Patent App., 0 | | |
| Method and Decision Feedback Equalizer Using Reference Voltage Division for PAM-4 C Kim, J Choi, S Park, S Kim, C Sim, H Shin KR Patent App., 0 | | |
