| A 68.6fsrms-total-integrated-jitter and 1.56μs-locking-time fractional-N bang-bang PLL based on type-II gear shifting and adaptive frequency switching SM Dartizio, F Buccoleri, F Tesolin, L Avallone, A Santiccioli, A Iesurum, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 20 | 2022 |
| A 12.9-to-15.1-GHz digital PLL based on a bang-bang phase detector with adaptively optimized noise shaping SM Dartizio, F Tesolin, M Mercandelli, A Santiccioli, A Shehata, S Karman, ... IEEE Journal of Solid-State Circuits 57 (6), 1723-1735, 2021 | 15 | 2021 |
| 32.3 A 12.9-to-15.1 GHz digital PLL based on a bang-bang phase detector with adaptively optimized noise shaping achieving 107.6 fs integrated jitter M Mercandelli, A Santiccioli, SM Dartizio, A Shehata, F Tesolin, S Karman, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 445-447, 2021 | 15 | 2021 |
| 4.3 A 76.7 fs-lntegrated-Jitter and− 71.9 dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering SM Dartizio, F Tesolin, G Castoro, F Buccoleri, L Lanzoni, M Rossoni, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 3-5, 2023 | 14 | 2023 |
| A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking … SM Dartizio, F Buccoleri, F Tesolin, L Avallone, A Santiccioli, A Iesurum, ... IEEE Journal of Solid-State Circuits 57 (12), 3538-3551, 2022 | 12 | 2022 |
| 4.5 a 9.25 GHz digital PLL with fractional-spur cancellation based on a multi-DTC topology G Castoro, SM Dartizio, F Tesolin, F Buccoleri, M Rossoni, D Cherniak, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 82-84, 2023 | 11 | 2023 |
| 32.8 A 98.4 fs-jitter 12.9-to-15.1 GHz PLL-based LO phase-shifting system with digital background phase-offset correction for integrated phased arrays A Santiccioli, M Mercandelli, SM Dartizio, F Tesolin, S Karman, A Shehata, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 456-458, 2021 | 10 | 2021 |
| A 18.9-22.3 GHz Dual-Core Digital PLL with On-Chip Power Combination for Phase Noise and Power Scalability S Karman, F Tesolin, A Dago, M Mercandelli, C Samori, S Levantino 2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 67-70, 2021 | 9 | 2021 |
| A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler F Buccoleri, SM Dartizio, F Tesolin, L Avallone, A Santiccioli, A Iesurum, ... 2022 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2022 | 5 | 2022 |
| A novel topology of coupled phase-locked loops S Karman, F Tesolin, S Levantino, C Samori IEEE Transactions on Circuits and Systems I: Regular Papers 68 (3), 989-997, 2020 | 5 | 2020 |
| A Low-Spur and Low-Jitter Fractional- Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering SM Dartizio, F Tesolin, G Castoro, F Buccoleri, M Rossoni, D Cherniak, ... IEEE Journal of Solid-State Circuits, 2023 | 4 | 2023 |
| A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner F Buccoleri, SM Dartizio, F Tesolin, L Avallone, A Santiccioli, A Iesurum, ... IEEE Journal of Solid-State Circuits 58 (3), 634-646, 2022 | 4 | 2022 |
| A novel LO phase-shifting system based on digital bang-bang PLLs with background phase-offset correction for integrated phased arrays F Tesolin, SM Dartizio, F Buccoleri, A Santiccioli, L Bertulessi, C Samori, ... IEEE Journal of Solid-State Circuits 58 (9), 2466-2477, 2023 | 2 | 2023 |
| SiGe BiCMOS building blocks for E-and D-band backhauling front-ends G Amendola, L Boccia, F Centurelli, P Chevalier, A Fonte, S Karman, ... 2021 16th European Microwave Integrated Circuits Conference (EuMIC), 113-116, 2022 | 1 | 2022 |
| Self-Biasing Dynamic Startup Circuit for Current-Biased Class-C Oscillators A Parisi, F Tesolin, M Mercandelli, L Bertulessi, AL Lacaita IEEE Microwave and Wireless Components Letters 31 (9), 1075-1078, 2021 | 1 | 2021 |
| A 59.3 fs Jitter and-62.1 dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector SM Dartizio, M Rossoni, F Tesolin, G Castoro, C Samori, AL Lacaita, ... 2024 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2024 | | 2024 |
| A 66.7 fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC P Salvi, SM Dartizio, M Rossoni, F Tesolin, G Castoro, AL Lacaita, ... 2024 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2024 | | 2024 |
| 10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion F Tesolin, SM Dartizio, G Castoro, F Buccoleri, M Rossoni, D Cherniak, ... 2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 198-200, 2024 | | 2024 |
| 10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and −252.4dB FoM M Rossoni, SM Dartizio, F Tesolin, G Castoro, R Dell’Orto, C Samori, ... 2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 188-190, 2024 | | 2024 |
| Progetto di PLL accoppiati a 20 GHz in tecnologia CMOS 55nm F TESOLIN Politecnico di Milano, 2018 | | 2018 |
