A multiple negative differential resistance heterojunction device and its circuit application to ternary static random access memory KH Kim, HY Park, J Shim, G Shin, M Andreev, J Koo, G Yoo, K Jung, ... Nanoscale horizons 5 (4), 654-662, 2020 | 73 | 2020 |
A charge-domain scalable-weight in-memory computing macro with dual-SRAM architecture for precision-scalable DNN accelerators E Lee, T Han, D Seo, G Shin, J Kim, S Kim, S Jeong, J Rhe, J Park, JH Ko, ... IEEE Transactions on Circuits and Systems I: Regular Papers 68 (8), 3305-3316, 2021 | 50 | 2021 |
Double negative differential transconductance characteristic: from device to circuit application toward quaternary inverter JH Lim, J Shim, BS Kang, G Shin, H Kim, M Andreev, KS Jung, KH Kim, ... Advanced Functional Materials 29 (48), 1905540, 2019 | 43 | 2019 |
A fully static true-single-phase-clocked dual-edge-triggered flip-flop for near-threshold voltage operation in IoT applications Y Lee, G Shin, Y Lee IEEE Access 8, 40232-40245, 2020 | 31 | 2020 |
Functionalized organic material platform for realization of ternary logic circuit J Jeon, MJ Kim, G Shin, M Lee, YJ Kim, BS Kim, Y Lee, JH Cho, S Lee ACS applied materials & interfaces 12 (5), 6119-6126, 2020 | 23 | 2020 |
An ultra-low-power fully-static contention-free flip-flop with complete redundant clock transition and transistor elimination G Shin, E Lee, J Lee, Y Lee, Y Lee IEEE Journal of Solid-State Circuits 56 (10), 3039-3048, 2021 | 20 | 2021 |
A 20F2 Area-Efficient Differential nand-Structured Physically Unclonable Function for Low-Cost IoT Security J Lee, M Kim, G Shin, Y Lee ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference (ESSCIRC), 1-4, 2019 | 10 | 2019 |
A static contention-free differential flip-flop in 28nm for low-voltage, low-power applications G Shin, E Lee, J Lee, Y Lee, Y Lee 2020 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2020 | 9 | 2020 |
A 20F2/Bit Current-Integration-Based Differential nand-Structured PUF for Stable and V/T Variation-Tolerant Low-Cost IoT Security J Lee, M Kim, M Jeong, G Shin, Y Lee IEEE Journal of Solid-State Circuits 57 (10), 2957-2968, 2022 | 7 | 2022 |
A differential flip-flop with static contention-free characteristics in 28 nm for low-voltage, low-power applications G Shin, E Lee, J Lee, Y Lee, Y Lee IEEE Journal of Solid-State Circuits 58 (5), 1496-1504, 2022 | 6 | 2022 |
A redundancy eliminated flip-flop in 28 nm for low-voltage low-power applications G Shin, E Lee, J Lee, Y Lee, Y Lee IEEE Solid-State Circuits Letters 3, 446-449, 2020 | 6 | 2020 |
A charge-domain computation-in-memory macro with versatile all-around-wire-capacitor for variable-precision computation and array-embedded DA/AD conversions G Shin, D Seo, J Kim, J Rhe, E Lee, S Kim, S Jeong, JH Ko, Y Lee ESSDERC 2021-IEEE 51st European Solid-State Device Research Conference …, 2021 | 5 | 2021 |
An RC Delay-Based Pressure-Sensing System With Energy-Efficient Bit-Level Oversampling Techniques for Implantable IOP Monitoring Systems D Seo, M Cho, M Jeong, G Shin, I Lee, D Blaauw, Y Lee IEEE Journal of Solid-State Circuits 58 (10), 2745-2756, 2023 | 4 | 2023 |
A 0.24 mmHg (1σ) resolution half-bridge-to-digital converter with RC delay-based pressure sensing and energy-efficient bit-level oversampling techniques for implantable … D Seo, M Cho, M Jeong, G Shin, I Lee, Y Lee 2022 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2022 | 1 | 2022 |
A Variation-Tolerant Differential Contention-Free Pulsed Latch with Wide Voltage Scalability G Shin, M Jeong, D Seo, S Han, Y Lee 2022 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2022 | 1 | 2022 |
Circuit for physically unclonable function and a method to generate private key for secure authentication using a physically unclonable function cell YM Lee, JM Lee, MS Kim, GC Shin US Patent 11,646,899, 2023 | | 2023 |
Complementary clock gate and low power flip-flop circuit including same YM Lee, GC Shin US Patent 11,621,706, 2023 | | 2023 |