| SRAM interleaving distance selection with a soft error failure model S Baeg, SJ Wen, R Wong IEEE Transactions on Nuclear Science 56 (4), 2111-2118, 2009 | 194 | 2009 |
| Low cost emulation scheme implemented via clock control using JTAG controller in a scan environment SH Baeg US Patent 5,812,562, 1998 | 176 | 1998 |
| Low-power ternary content-addressable memory design using a segmented match line S Baeg IEEE Transactions on Circuits and Systems I: Regular Papers 55 (6), 1485-1494, 2008 | 106 | 2008 |
| Hybrid partitioned SRAM-based ternary content addressable memory Z Ullah, K Ilgon, S Baeg IEEE Transactions on Circuits and Systems I: Regular Papers 59 (12), 2969-2979, 2012 | 84 | 2012 |
| Minimizing soft errors in TCAM devices: A probabilistic approach to determining scrubbing intervals S Baeg, SJ Wen, R Wong IEEE Transactions on Circuits and Systems I: Regular Papers 57 (4), 814-822, 2009 | 69 | 2009 |
| Experiments and root cause analysis for active-precharge hammering fault in DDR3 SDRAM under 3× nm technology K Park, C Lim, D Yun, S Baeg Microelectronics reliability 57, 39-46, 2016 | 68 | 2016 |
| Resource-efficient SRAM-based ternary content addressable memory A Ahmed, K Park, S Baeg IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (4 …, 2016 | 61 | 2016 |
| Protection of memories suffering MCUs through the selection of the optimal interleaving distance P Reviriego, JA Maestro, S Baeg, SJ Wen, R Wong IEEE Transactions on Nuclear Science 57 (4), 2124-2128, 2010 | 58 | 2010 |
| A quatro-based 65-nm flip-flop circuit for soft-error resilience YQ Li, HB Wang, R Liu, L Chen, I Nofal, ST Shi, AL He, G Guo, SH Baeg, ... IEEE Transactions on Nuclear Science 64 (6), 1554-1561, 2017 | 54 | 2017 |
| An SEU-tolerant DICE latch design with feedback transistors HB Wang, YQ Li, L Chen, LX Li, R Liu, S Baeg, N Mahatme, BL Bhuva, ... IEEE Transactions on Nuclear Science 62 (2), 548-554, 2015 | 48 | 2015 |
| Clock generation for testing of integrated circuits SH Baeg, E Yu US Patent 5,805,608, 1998 | 45 | 1998 |
| Structure and method for SDRAM dynamic self refresh entry and exit using JTAG A Qureshi, SH Baeg US Patent 5,793,776, 1998 | 40 | 1998 |
| Adaptable scan chains for debugging and manufacturing test purposes SH Baeg US Patent 6,018,815, 2000 | 39 | 2000 |
| Statistical distributions of row-hammering induced failures in DDR3 components K Park, D Yun, S Baeg Microelectronics Reliability 67, 143-149, 2016 | 38 | 2016 |
| Supply voltage dependence of heavy ion induced SEEs on 65 nm CMOS bulk SRAMs Q Wu, Y Li, L Chen, A He, G Guo, SH Baeg, H Wang, R Liu, L Li, SJ Wen, ... IEEE Transactions on Nuclear Science 62 (4), 1898-1904, 2015 | 38 | 2015 |
| Evaluation of SEU performance of 28-nm FDSOI flip-flop designs HB Wang, JS Kauppila, K Lilja, M Bounasser, L Chen, M Newton, YQ Li, ... IEEE Transactions on Nuclear Science 64 (1), 367-373, 2016 | 33 | 2016 |
| Active-precharge hammering on a row induced failure in ddr3 sdrams under 3× nm technology K Park, S Baeg, SJ Wen, R Wong 2014 IEEE International Integrated Reliability Workshop Final Report (IIRW …, 2014 | 29 | 2014 |
| An area efficient stacked latch design tolerant to SEU in 28 nm FDSOI technology HB Wang, L Chen, R Liu, YQ Li, JS Kauppila, BL Bhuva, K Lilja, SJ Wen, ... IEEE Transactions on Nuclear Science 63 (6), 3003-3009, 2016 | 28 | 2016 |
| Single-event transient sensitivity evaluation of clock networks at 28-nm CMOS technology HB Wang, N Mahatme, L Chen, M Newton, YQ Li, R Liu, M Chen, ... IEEE Transactions on Nuclear Science 63 (1), 385-391, 2016 | 25 | 2016 |
| A 65 nm temporally hardened flip-flop circuit YQ Li, HB Wang, R Liu, L Chen, I Nofal, QY Chen, AL He, G Guo, ... IEEE Transactions on Nuclear Science 63 (6), 2934-2940, 2016 | 24 | 2016 |
