| Low-cost AES-128 implementation for edge devices in IoT applications S Shanthi Rekha, P Saravanan Journal of Circuits, Systems and Computers 28 (04), 1950062, 2019 | 33 | 2019 |
| Novel reversible design of advanced encryption standard cryptographic algorithm for wireless sensor networks P Saravanan, P Kalpana Wireless Personal Communications 100, 1427-1458, 2018 | 23 | 2018 |
| Authenticated key agreement protocol for secure communication establishment in vehicle-to-grid environment with FPGA implementation V Sureshkumar, P Chinnaraj, P Saravanan, R Amin, JJPC Rodrigues IEEE Transactions on Vehicular Technology 71 (4), 3470-3479, 2022 | 21 | 2022 |
| A novel and systematic approach to implement reversible gates in quantum dot cellular automata P Saravanan, P Kalpana Quantum 2 (5), 15, 2013 | 20 | 2013 |
| Survey on power analysis attacks and its impact on intelligent sensor networks SR Shanmugham, S Paramasivam IET Wireless Sensor Systems 8 (6), 295-304, 2018 | 18 | 2018 |
| An efficient hardware Trojan detection approach adopting testability based features M Priyadharshini, P Saravanan 2020 IEEE International Test Conference India, 1-5, 2020 | 10 | 2020 |
| Power analysis attack using neural networks with wavelet transform as pre-processor P Saravanan, P Kalpana, V Preethisri, V Sneha 18th International Symposium on VLSI Design and Test, 1-6, 2014 | 10 | 2014 |
| An energy efficient XOR gate implementation resistant to power analysis attacks P Saravanan, P Kalpana J. Eng. Sci. Technol 10 (1), 1275-1292, 2015 | 9 | 2015 |
| A novel approach to attack smartcards using machine learning method P Saravanan, P Kalpana NISCAIR-CSIR, India, 2017 | 8 | 2017 |
| Power analysis attack on 8051 microcontrollers P Saravanan, N Rajadurai, P Kalpana 2014 IEEE International Conference on Computational Intelligence and …, 2014 | 8 | 2014 |
| Design and implementation of efficient vedic multiplier using reversible logic P Saravanan, P Chandrasekar, L Chandran, N Sriram, P Kalpana Progress in VLSI Design and Test: 16th International Symposium, VDAT 2012 …, 2012 | 8 | 2012 |
| Performance Analysis of Reversible Finite Field Arithmetic Architectures Over GF(p) and GF(2m) in Elliptic Curve Cryptography P Saravanan, P Kalpana Journal of Circuits, Systems and Computers 24 (08), 1550122, 2015 | 7 | 2015 |
| Maximal overlap discrete wavelet transform‐based power trace alignment algorithm against random delay countermeasure S Paramasivam, SA PL, P Sathyamoorthi Etri Journal 44 (3), 512-523, 2022 | 6 | 2022 |
| An efficient ASIC implementation of CLEFIA encryption/decryption algorithm with novel S-box architectures P Saravanan, SS Rani, SS Rekha, HS Jatana 2019 IEEE 1st International Conference on Energy, Systems and Information …, 2019 | 6 | 2019 |
| Low cost circuit level implementation of PRESENT-80 S-BOX S Shanthi Rekha, P Saravanan VLSI Design and Test: 21st International Symposium, VDAT 2017, Roorkee …, 2017 | 6 | 2017 |
| Energy efficient reversible building blocks resistant to power analysis attacks P Saravanan, P Kalpana Journal of Circuits, Systems and Computers 23 (09), 1450127, 2014 | 6 | 2014 |
| A High-Throughput ASIC implementation of Configurable Advanced Encryption Standard (AES) Processor P Saravanan, N RenukaDevi, G Swathi, P Kalpana IJCA Special Issue on Network Security and Cryptography, NSC, 2011 | 6 | 2011 |
| A Novel Approach to Detect Hardware Malware Using Hamming Weight Model and One Class Support Vector Machine P Saravanan, BM Mehtre International Symposium on VLSI Design and Test 2018, 159-172, 2019 | 5 | 2019 |
| Quantum circuit design of rectangle lightweight cipher P Saravanan, J Jenitha, SR Aasish, S Sanjana 2021 25th International Symposium on VLSI Design and Test (VDAT), 1-4, 2021 | 4 | 2021 |
| BSAPM: BlockChain based secured authentication protocol for large scale WSN with FPGA implementation M Abdussami, R Amin, P Saravanan, S Vollala Computer Communications 209, 63-77, 2023 | 3 | 2023 |
