| A multiobjective optimization based fast and robust design methodology for low power and low phase noise current starved VCO PK Rout, DP Acharya, G Panda IEEE Transactions on Semiconductor Manufacturing 27 (1), 43-50, 2013 | 72 | 2013 |
| A high stable 8T-SRAM with bit interleaving capability for minimization of soft error rate UN Debasish Nayak, Debiprasad Priyabrata Acharya, , Prakash Kumar Rout, Microelectronics Journal 73, Pages 43–51, 2018 | 33 | 2018 |
| Smart power theft detection system NK Mucheli, U Nanda, D Nayak, PK Rout, SK Swain, SK Das, SM Biswal 2019 Devices for Integrated Circuit (DevIC), 302-305, 2019 | 20 | 2019 |
| Design of LC VCO for optimal figure of merit performance using CMODE PK Rout, UK Nanda, DP Acharya, G Panda 2012 1st International Conference on Recent Advances in Information …, 2012 | 18 | 2012 |
| A novel charge recycle read write assist technique for energy efficient and fast 20 nm 8T-SRAM array D Nayak, DP Acharya, PK Rout, U Nanda Solid-State Electronics 148, 43-50, 2018 | 17 | 2018 |
| Design of CMOS ring oscillator using CMODE PK Rout, DP Acharya 2011 international conference on energy, automation and signal, 1-6, 2011 | 17 | 2011 |
| Analysis and design of 1 GHz PLL for fast phase and frequency acquisition PK Rout, BP Panda, DP Acharya, G Panda International Journal of Signal and Imaging Systems Engineering 7 (1), 30-37, 2014 | 16 | 2014 |
| Design of low-leakage and high writable proposed SRAM cell structure D Nayak, DP Acharya, PK Rout, KK Mahapatra 2014 International Conference on Electronics and Communication Systems …, 2014 | 14 | 2014 |
| Design of a novel current starved VCO via constrained geometric programming BP Panda, PK Rout, DP Acharya, G Panda | 12 | 2011 |
| Digital circuit placement in FPGA based on efficient particle swarm optimization techniques PK Rout, DP Acharya, G Panda 2010 5th International Conference on Industrial and Information Systems, 224-227, 2010 | 11 | 2010 |
| A novel indirect read technique based SRAM with ability to charge recycle and differential read for low power consumption, high stability and performance D Nayak, PK Rout, S Sahu, DP Acharya, U Nanda, D Tripthy Microelectronics Journal 97, 104723, 2020 | 10 | 2020 |
| Study of recent charge pump circuits in phase locked loop U Nanda, J Sarangi, PK Rout International Journal of Modern Education and Computer Science 8 (8), 59, 2016 | 8 | 2016 |
| Novel PSO based FPGA placement techniques PK Rout, DP Acharya, G Panda 2010 International Conference on Computer and Communication Technology …, 2010 | 8 | 2010 |
| Advances in analog integrated circuit optimization: a survey PK Rout, DP Acharya, U Nanda Handbook of research on applied optimization methodologies in manufacturing …, 2018 | 7 | 2018 |
| A novel low power 3T inverter PK Rout, D Nayak, DP Acharya 2013 International Conference on Advanced Electronic Systems (ICAES), 221-224, 2013 | 7 | 2013 |
| Fast physical design of CMOS ROs for optimal performance using constrained NSGA-II PK Rout, DP Acharya AEU-International Journal of Electronics and Communications 69 (9), 1233-1242, 2015 | 6 | 2015 |
| Process corner variation aware design of low power current starved VCO power PK Rout, DP Acharya, G Panda, D Nayak 2014 International Conference on Electronics and Communication Systems …, 2014 | 6 | 2014 |
| Influence of oxide thickness variation on analog and RF performances of SOI FinFET D Tripathy, DP Acharya, PK Rout, SM Biswal Facta Universitatis, Series: Electronics and Energetics 35 (1), 001-011, 2022 | 5 | 2022 |
| Constrained multiobjective optimization based design of CMOS ring oscillator PK Rout, DP Acharya, G Panda 2014 International Conference on Computer Communication and Informatics, 1-5, 2014 | 4 | 2014 |
| A novel driver less SRAM with indirect read for low energy consumption and read noise elimination D Nayak, U Nanda, PK Rout, SM Biswal, D Tripthy, SK Swain, B Baral, ... 2019 Devices for Integrated Circuit (DevIC), 314-317, 2019 | 3 | 2019 |
Debasish NayakAssociate Professor, Dept. of Electronics Engineering, Silicon Institute of Technology, Bhubaneswar在 silicon.ac.in 的电子邮件经过验证
Debasish NayakAssociate Professor, Dept. of Electronics Engineering, Silicon Institute of Technology, Bhubaneswar在 silicon.ac.in 的电子邮件经过验证
Prof. Ganapati Panda (G. Panda)C V Raman Global University-Odisha在 cgu-odisha.ac.in 的电子邮件经过验证