S2cbench: Synthesizable systemc benchmark suite for high-level synthesis BC Schafer, A Mahapatra IEEE Embedded Systems Letters 6 (3), 53-56, 2014 | 185 | 2014 |
High-level synthesis design space exploration: Past, present, and future BC Schafer, Z Wang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 160 | 2019 |
What to lock? Functional and parametric locking M Yasin, A Sengupta, BC Schafer, Y Makris, O Sinanoglu, J Rajendran Proceedings of the on Great Lakes Symposium on VLSI 2017, 351-356, 2017 | 150 | 2017 |
Machine learning predictive modelling high-level synthesis design space exploration BC Schafer, K Wakabayashi IET computers & digital techniques 6 (3), 153-159, 2012 | 95 | 2012 |
Adaptive simulated annealer for high level synthesis design space exploration B Carrion Schafer, T Takenaka, K Wakabayashi VLSI Design, Automation and Test, 2009. VLSI-DAT'09. International Symposium …, 2009 | 84* | 2009 |
Divide and conquer high-level synthesis design space exploration B Carrion Schafer, K Wakabayashi ACM Transactions on Design Automation of Electronic Systems (TODAES) 17 (3), 29, 2012 | 77* | 2012 |
Machine-learning based simulated annealer method for high level synthesis design space exploration A Mahapatra, B Carrion Schafer Electronic System Level Synthesis Conference (ESLsyn), Proceedings of the …, 2014 | 68 | 2014 |
Exposing approximate computing optimizations at different levels: From behavioral to gate-level S Xu, BC Schafer IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (11 …, 2017 | 67 | 2017 |
Efficient and reliable high-level synthesis design space explorer for FPGAs D Liu, BC Schafer 2016 26th International Conference on Field Programmable Logic and …, 2016 | 60 | 2016 |
Design space exploration acceleration through operation clustering B Carrion Schafer, K Wakabayashi Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2010 | 52* | 2010 |
Machine leaming to set meta-heuristic specific parameters for high-level synthesis design space exploration Z Wang, BC Schafer 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 50 | 2020 |
Probabilistic multiknob high-level synthesis design space exploration acceleration BC Schafer IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 49 | 2015 |
Accelerating FPGA prototyping through predictive model-based HLS design space exploration S Liu, FCM Lau, BC Schafer Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 43 | 2019 |
Hardware Trojan detection in behavioral intellectual properties (IP's) using property checking techniques N Veeranna, BC Schafer IEEE Transactions on Emerging Topics in Computing 5 (4), 576-585, 2016 | 36 | 2016 |
Design obfuscation through selective post-fabrication transistor-level programming MM Shihab, J Tian, GR Reddy, B Hu, W Swartz, BC Schaefer, C Sechen, ... 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 528-533, 2019 | 35 | 2019 |
Functional obfuscation of hardware accelerators through selective partial design extraction onto an embedded fpga B Hu, J Tian, M Shihab, GR Reddy, W Swartz, Y Makris, BC Schaefer, ... Proceedings of the 2019 on Great Lakes Symposium on VLSI, 171-176, 2019 | 33 | 2019 |
Hotspots elimination and temperature flattening in VLSI circuits B Carrion Schafer, T Kim Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 16 (11 …, 2008 | 31* | 2008 |
Parallel high-level synthesis design space exploration for behavioral ips of exact latencies BC Schafer ACM Transactions on Design Automation of Electronic Systems (TODAES) 22 (4 …, 2017 | 30 | 2017 |
“All-in-C” Behavioral Synthesis and Verification with CyberWorkBench K Wakabayashi, B Carrion Schafer High-Level Synthesis, 113-127, 2008 | 30* | 2008 |
Acceleration of the discrete element method (DEM) on a reconfigurable co-processor BC Schäfer, SF Quigley, AHC Chan Computers & Structures 82 (20-21), 1707-1718, 2004 | 29 | 2004 |