| Pymtl3: A python framework for open-source hardware modeling, generation, simulation, and verification S Jiang, P Pan, Y Ou, C Batten IEEE Micro 40 (4), 58-66, 2020 | 61 | 2020 |
| Ultra-elastic cgras for irregular loop specialization C Torng, P Pan, Y Ou, C Tan, C Batten 2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021 | 55 | 2021 |
| PyOCN: A unified framework for modeling, testing, and evaluating on-chip networks C Tan, Y Ou, S Jiang, P Pan, C Torng, S Agwa, C Batten 2019 IEEE 37th International Conference on Computer Design (ICCD), 437-445, 2019 | 19 | 2019 |
| Implementing low-diameter on-chip networks for manycore processors using a tiled physical design methodology Y Ou, S Agwa, C Batten 2020 14th IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 1-8, 2020 | 12 | 2020 |
| Feasibility of fingertip oscillometric blood pressure measurement: Model-based analysis and experimental validation J Liu, CG Sodini, Y Ou, B Yan, YT Zhang, N Zhao IEEE Journal of Biomedical and Health Informatics 24 (2), 533-542, 2019 | 12 | 2019 |
| PyH2: Using PyMTL3 to create productive and open-source hardware testing methodologies S Jiang, Y Ou, P Pan, K Cheng, Y Zhang, C Batten IEEE Design & Test 38 (2), 53-61, 2020 | 9 | 2020 |
| Comparisons of oscillometric blood pressure measurements at different sites of the upper limb J Liu, Y Ou, BP Yan, C Sodini, N Zhao 2018 40th Annual International Conference of the IEEE Engineering in …, 2018 | 8 | 2018 |
| CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm2 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA TJ Chang, A Li, F Gao, T Ta, G Tziantzioulis, Y Ou, M Wang, J Tu, K Xu, ... 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023 | 4 | 2023 |
| Big. VLITTLE: On-demand data-parallel acceleration for mobile systems on chip T Ta, K Al-Hawaj, N Cebry, Y Ou, E Hall, C Golden, C Batten 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), 181-198, 2022 | 4 | 2022 |
| CIFER: A Cache-Coherent 12nm 16mm 2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm 2 Synthesizable eFPGA A Li, TJ Chang, F Gao, T Ta, G Tziantzioulis, Y Ou, M Wang, J Tu, K Xu, ... IEEE Solid-State Circuits Letters, 2023 | 3 | 2023 |
| UMOC: Unified Modular Ordering Constraints to Unify Cycle-and Register-Transfer-Level Modeling S Jiang, Y Ou, P Pan, C Batten 2021 58th ACM/IEEE Design Automation Conference (DAC), 883-888, 2021 | 2 | 2021 |
| Symbolic Elaboration: Checking Generator Properties in Dynamic Hardware Description Languages P Pan, S Jiang, Y Ou, C Batten Proceedings of the 21st ACM-IEEE International Conference on Formal Methods …, 2023 | 1 | 2023 |
| Towards gradually typed hardware description languages P Pan, S Jiang, Y Ou, C Batten Rem 504, 0, 2023 | 1 | 2023 |
| ICED: An Integrated CGRA Framework Enabling DVFS-Aware Acceleration C Tan, M Jiang, D Patil, Y Ou, Z Li, L Ju, T Mitra, H Park, A Tumeo, ... | | |
Christopher BattenCornell University在 cornell.edu 的电子邮件经过验证
