| Convolution engine: balancing efficiency & flexibility in specialized computing W Qadeer, R Hameed, O Shacham, P Venkatesan, C Kozyrakis, ... Proceedings of the 40th Annual International Symposium on Computer …, 2013 | 318 | 2013 |
| CPU DB: Recording Microprocessor History MH Andrew Danowitz, Kyle Kelley, James Mao, John P Queue 10 (4), 10, 2012 | 292* | 2012 |
| Years of microprocessor trend data K Rupp by karlrupp. net.[Online, 42 | 153 | 42 |
| Rethinking digital design: Why design must change O Shacham, O Azizi, M Wachs, W Qadeer, Z Asgar, K Kelley, ... IEEE micro 30 (6), 9-24, 2010 | 132 | 2010 |
| Chip multiprocessor generator: automatic generation of custom and heterogeneous compute platforms O Shacham Stanford University, 2011 | 89 | 2011 |
| Avoiding game over: Bringing design to the next level O Shacham, M Wachs, A Danowitz, S Galal, J Brunhaver, W Qadeer, ... Proceedings of the 49th Annual Design Automation Conference, 623-629, 2012 | 61 | 2012 |
| Virtual linebuffers for image signal processors Q Zhu, O Shacham, JR Redgrave, DF Finchelstein, A Meixner US Patent 9,749,548, 2017 | 54 | 2017 |
| Architecture for high performance, power efficient, programmable image processing Q Zhu, O Shacham, A Meixner, JR Redgrave, DF Finchelstein, ... US Patent 9,965,824, 2018 | 44 | 2018 |
| Convolutional neural network on programmable two dimensional image processor O Shacham, D Patterson, WR Mark, A Meixner, DF Finchelstein, ... US Patent 10,546,211, 2020 | 41 | 2020 |
| FPU generator for design space exploration S Galal, O Shacham, JS Brunhaver II, J Pu, A Vassiliev, M Horowitz 2013 IEEE 21st Symposium on Computer Arithmetic, 25-34, 2013 | 39 | 2013 |
| Line buffer unit for image processor N Desai, A Meixner, Q Zhu, JR Redgrave, O Shacham, DF Finchelstein US Patent 9,756,268, 2017 | 35 | 2017 |
| A memory system design framework: creating smart memories A Firoozshahian, A Solomatnikov, O Shacham, Z Asgar, S Richardson, ... Proceedings of the 36th annual international symposium on Computer …, 2009 | 35 | 2009 |
| Verification of chip multiprocessor memory systems using a relaxed scoreboard O Shacham, M Wachs, A Solomatnikov, A Firoozshahian, S Richardson, ... 2008 41st IEEE/ACM International Symposium on Microarchitecture, 294-305, 2008 | 35 | 2008 |
| System and method for a chip generator O Shacham, M Horowitz, S Richardson US Patent 8,966,413, 2015 | 34 | 2015 |
| Design automation framework for application-specific logic-in-memory blocks Q Zhu, K Vaidyanathan, O Shacham, M Horowitz, L Pileggi, F Franchetti 2012 IEEE 23rd International Conference on Application-Specific Systems …, 2012 | 34 | 2012 |
| Two dimensional shift array for image processor O Shacham, JR Redgrave, A Meixner, Q Zhu, DF Finchelstein, ... US Patent 9,769,356, 2017 | 30 | 2017 |
| Energy efficient processor core architecture for image processor A Meixner, JR Redgrave, O Shacham, DF Finchelstein, Q Zhu US Patent 9,772,852, 2017 | 29 | 2017 |
| Pixel visual core: Google’s fully programmable image vision and AI processor for mobile devices J Redgrave, A Meixner, N Goulding-Hotta, A Vasilyev, O Shacham Proc. IEEE Hot Chips Symp.(HCS), 1-18, 2018 | 28 | 2018 |
| Sheet generator for image processor A Meixner, JR Redgrave, O Shacham, Q Zhu, DF Finchelstein US Patent 10,291,813, 2019 | 27 | 2019 |
| Virtual image processor instruction set architecture (isa) and memory model and exemplary target hardware having a two-dimensional shift array structure A Meixner, O Shacham, D Patterson, DF Finchelstein, Q Zhu, ... US Patent 10,095,479, 2018 | 27 | 2018 |
Albert Meixner在 nuro.ai 的电子邮件经过验证
