X-SRAM: Enabling in-memory Boolean computations in CMOS static random access memories A Agrawal, A Jaiswal, C Lee, K Roy IEEE Transactions on Circuits and Systems I: Regular Papers 65 (12), 4219-4232, 2018 | 288 | 2018 |
8T SRAM cell as a multibit dot-product engine for beyond von Neumann computing A Jaiswal, I Chakraborty, A Agrawal, K Roy IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (11 …, 2019 | 174 | 2019 |
Xcel-RAM: Accelerating binary neural networks in high-throughput SRAM compute arrays A Agrawal, A Jaiswal, D Roy, B Han, G Srinivasan, A Ankit, K Roy IEEE Transactions on Circuits and Systems I: Regular Papers 66 (8), 3064-3076, 2019 | 119 | 2019 |
IMAC: In-memory multi-bit multiplication and accumulation in 6T SRAM array M Ali, A Jaiswal, S Kodge, A Agrawal, I Chakraborty, K Roy IEEE Transactions on Circuits and Systems I: Regular Papers 67 (8), 2521-2531, 2020 | 108 | 2020 |
Resistive crossbars as approximate hardware building blocks for machine learning: Opportunities and challenges I Chakraborty, M Ali, A Ankit, S Jain, S Roy, S Sridharan, A Agrawal, ... Proceedings of the IEEE 108 (12), 2276-2310, 2020 | 84 | 2020 |
In-memory computing in emerging memory technologies for machine learning: An overview K Roy, I Chakraborty, M Ali, A Ankit, A Agrawal 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 62 | 2020 |
Design of a low-voltage analog-to-digital converter using voltage-controlled stochastic switching of low barrier nanomagnets I Chakraborty, A Agrawal, K Roy IEEE Magnetics Letters 9, 1-5, 2018 | 39 | 2018 |
IMPULSE: A 65nm Digital Compute-in-Memory Macro with Fused Weights and Membrane Potential for Spike-based Sequential Learning Tasks A Agrawal, M Ali, M Koo, N Rathi, A Jaiswal, K Roy IEEE Solid-State Circuits Letters 4, 137-140, 2021 | 28 | 2021 |
Circuits and architectures for in-memory computing-based machine learning accelerators A Ankit, I Chakraborty, A Agrawal, M Ali, K Roy IEEE Micro 40 (6), 8-22, 2020 | 28 | 2020 |
X-CHANGR: Changing memristive crossbar mapping for mitigating line-resistance induced accuracy degradation in deep neural networks A Agrawal, C Lee, K Roy arXiv preprint arXiv:1907.00285, 2019 | 26 | 2019 |
i-SRAM: Interleaved Wordlines for Vector Boolean Operations Using SRAMs A Jaiswal, A Agrawal, MF Ali, S Sharmin, K Roy IEEE Transactions on Circuits and Systems I: Regular Papers 67 (12), 4651-4659, 2020 | 25 | 2020 |
In-situ, In-Memory Stateful Vector Logic Operations based on Voltage Controlled Magnetic Anisotropy A Jaiswal, A Agrawal, K Roy Scientific reports 8 (1), 5738, 2018 | 25 | 2018 |
Cuffless BP measurement using a correlation study of pulse transient time and heart rate N Kumar, A Agrawal, S Deb 2014 International Conference on Advances in Computing, Communications and …, 2014 | 25 | 2014 |
Mimicking leaky-integrate-fire spiking neuron using automotion of domain walls for energy-efficient brain-inspired computing A Agrawal, K Roy IEEE Transactions on Magnetics 55 (1), 1-7, 2018 | 24 | 2018 |
A 35.5-127.2 tops/w dynamic sparsity-aware reconfigurable-precision compute-in-memory sram macro for machine learning M Ali, I Chakraborty, U Saxena, A Agrawal, A Ankit, K Roy IEEE Solid-State Circuits Letters 4, 129-132, 2021 | 23 | 2021 |
CASH-RAM: Enabling in-memory computations for edge inference using charge accumulation and sharing in standard 8T-SRAM arrays A Agrawal, A Kosta, S Kodge, DE Kim, K Roy IEEE Journal on Emerging and Selected Topics in Circuits and Systems 10 (3 …, 2020 | 22 | 2020 |
SPARE: Spiking neural network acceleration using ROM-embedded RAMs as in-memory-computation primitives A Agrawal, A Ankit, K Roy IEEE Transactions on Computers 68 (8), 1190-1200, 2018 | 22 | 2018 |
RAMANN: in-SRAM differentiable memory computations for memory-augmented neural networks M Ali, A Agrawal, K Roy Proceedings of the ACM/IEEE International Symposium on Low Power Electronics …, 2020 | 21 | 2020 |
Neural computing with magnetoelectric domain-wall-based neurosynaptic devices A Jaiswal, A Agrawal, P Panda, K Roy IEEE Transactions on Magnetics 57 (2), 1-9, 2020 | 18* | 2020 |
Multi-bit dot product engine AR Jaiswal, A Agrawal, K Roy, I Chakraborty US Patent 10,825,510, 2020 | 14 | 2020 |