| Data compression using Shannon-fano algorithm implemented by VHDL M Vaidya, ES Walia, A Gupta 2014 International Conference on Advances in Engineering & Technology …, 2014 | 16 | 2014 |
| Trench IGBT with stepped doped collector for low energy loss M Vaidya, A Naugarhiya, S Verma Semiconductor Science and Technology 35 (2), 025015, 2020 | 10 | 2020 |
| Lateral variation-doped insulated gate bipolar transistor for low on-state voltage with low loss M Vaidya, A Naugarhiya, S Verma, GP Mishra IEEE Electron Device Letters 41 (6), 888-891, 2020 | 8 | 2020 |
| High speed bootstrapping generic voltage level shifter M Vaidya, A Naugarhiya, S Verma 2018 Second International Conference on Advances in Electronics, Computers …, 2018 | 5 | 2018 |
| Collector Engineered Bidirectional Insulated Gate Bipolar Transistor With Low Loss M Vaidya, A Naugarhiya, S Verma, GP Mishra IEEE Transactions on Electron Devices 69 (3), 1604-1607, 2022 | 4 | 2022 |
| A low-loss variable-doped trench-insulated gate bipolar transistor with reduced on-state voltage M Vaidya, A Naugarhiya, S Verma, GP Mishra Semiconductor Science and Technology 36 (7), 075002, 2021 | 3 | 2021 |
| An Efficient Hardware Architecture for Route Discovery in AODV for a Sensor Node S Hafizullah, S Verma, M Vaidya, A Naugarhiya 9th Annual Information Technology, Electromechanical Engineering and …, 2019 | 3 | 2019 |
| 1.2 kV Stepped Oxide Trench Insulated Gate Bipolar Transistor with Low Loss for Fast Switching Application M Vaidya, A Naugarhiya, S Verma, GP Mishra ECS Journal of Solid State Science and Technology 11 (11), 111008, 2022 | 2 | 2022 |
| Slotted CSMA/CA Simulation in Verilog A Chakradhari, S Tamrakar, R Basant, M Vaidya, S Majumdar, ... | 2 | 2016 |
| Feature level fusion of palm print and fingerprint modalities using Discrete Cosine Transform A Gupta, E Walia, M Vaidya 2014 International Conference on Advances in Engineering & Technology …, 2015 | 2* | 2015 |
| Design and Analysis of Improved IGBT with Embedded p+ in N-Buffer Layer M Vaidya, A Naugarhiya, S Verma 2019 IEEE 16th India Council International Conference (INDICON), 1-4, 2019 | 1 | 2019 |
| Missing Trigger Circuit Action and Device Engineering for Conventional Nanoscale SCR M Goyal, M Chaturvedi, R Kumar, M Vaidya, M Shrivastava 2024 IEEE International Reliability Physics Symposium (IRPS), 1-6, 2024 | | 2024 |
| Load-line Dependent Current Filament Dynamics in N anoscale SCR Devices M Goyal, M Chaturvedi, R Kumar, M Vaidya, M Shrivastava 2024 IEEE International Reliability Physics Symposium (IRPS), 1-6, 2024 | | 2024 |
| Low Loss Gate Engineered Superjunction Insulated Gate Bipolar Transistor for High Speed Application SP Behera, M Vaidya, A Naugarhiya 2024 37th International Conference on VLSI Design and 2024 23rd …, 2024 | | 2024 |
| Insulated Gate Bipolar Transistors with Deep Trench Technology for Low Loss Switching Application A Naugarhiya, C Das, M Vaidya 2023 International Conference on Modeling, Simulation & Intelligent …, 2023 | | 2023 |
| Low Loss Enabled Semi-superjunction 4H-SiC IGBT for High Voltage and Current Application M Vaidya, A Naugarhiya, S Verma, GP Mishra International Symposium on VLSI Design and Test, 53-64, 2022 | | 2022 |
| Design And Analysis Of Trench Superjunction Insulated Gate Bipolar Transistor Limitations And Solutions M Vaidya Raipur, 2022 | | 2022 |
| Lateral variation doped wide bottom trench gate IGBT for reduced on-resistance with improved gate charge M Vaidya, A Naugarhiya, S Verma Materials Today: Proceedings 46, 4587-4592, 2021 | | 2021 |
| Comparative Analysis for Low Power and High Speed CMOS Voltage Level Shifter M Vaidya, A Dwivedi, S Singhal, R Singh | | 2014 |
| VLSID 2024 SP Behera, M Vaidya, A Naugarhiya | | |
Dr. Aditya Dinesh GuptaPostDoct in CAIR, University of Agder, Norway在 students.vnit.ac.in 的电子邮件经过验证
