| 15.5 A 0.6 V 1.17 ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology SJ Kim, W Kim, M Song, J Kim, T Kim, H Park 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 60 | 2015 |
| Phase-locked-loop circuit having a pre-calibration function and method of pre-calibrating the same SM Ha, WS Kim US Patent 7,876,136, 2011 | 42 | 2011 |
| A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range W Kim, J Park, J Kim, T Kim, HJ Park, DK Jeong 2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013 | 40 | 2013 |
| Voltage-controlled oscillators with controlled operating range and related bias circuits and methods WS Kim, JH Kim US Patent 7,233,214, 2007 | 37 | 2007 |
| Layout synthesis and loop parameter optimization of a low-jitter all-digital pixel clock generator W Kim, J Park, H Park, DK Jeong IEEE Journal of Solid-State Circuits 49 (3), 657-672, 2014 | 35 | 2014 |
| A 1.2 mW 0.02 mm2 2GHz current-controlled PLL based on a self-biased voltage-to-current converter WY Jung, HC Choi, CW Jeong, KY Kim, WS Kim, HJ Jeon, GS Koo, ... 2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007 | 35 | 2007 |
| A 0.015-mmInductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology GS Jeong, W Kim, J Park, T Kim, H Park, DK Jeong IEEE Transactions on Circuits and Systems II: Express Briefs 64 (6), 655-659, 2015 | 29 | 2015 |
| A 0.009mm2 2.06mW 32-to-2000MHz 2nd-order ΔΣ analogous bang-bang digital PLL with feed-forward delay-locked and phase-locked operations in 14nm FinFET technology M Song, T Kim, J Kim, W Kim, SJ Kim, Hojin Park ISSCC, pp.1,3, 22-26, 2015 | 23* | 2015 |
| Phase-locked loop circuit having phase lock detection function and method for detecting phase lock thereof WS Kim, PJ Jeon US Patent 7,116,145, 2006 | 18 | 2006 |
| Phase-locked loop circuit, delay-locked loop circuit and method of tuning output frequencies of the same WS Kim US Patent 7,495,488, 2009 | 16 | 2009 |
| A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC M Song, YH Kwak, S Ahn, W Kim, BH Park, C Kim 2009 IEEE Custom Integrated Circuits Conference, 243-246, 2009 | 13 | 2009 |
| A 0.02mm2 fully synthesizable period-jitter sensor using stochastic TDC without reference clock and calibration in 10nm CMOS technology K Choo, H Kim, W Kim, J Kim, T Kim, H Ko 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 120-122, 2018 | 10 | 2018 |
| Digital phase locked loop and operating method of digital phase locked loop W Yu, W Kim, J Kim, T Kim, K Choo US Patent 10,158,367, 2018 | 7 | 2018 |
| A crystal-less programmable clock generator with RC-LC hybrid oscillator for GHz applications in 14 nm FinFET CMOS J Hwang, GS Jeong, SH Chu, W Kim, T Kim, DK Jeong 2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and …, 2018 | 7 | 2018 |
| Clock multiplier and method of multiplying a clock WS Kim US Patent 7,636,002, 2009 | 7 | 2009 |
| Clock generator to reduce long term jitter CW Kim, WS Kim, MY Song, JJ Park, JH Kim, YH Kwak US Patent 8,149,030, 2012 | 6 | 2012 |
| Clock multiplier and clock generator having the same WS Kim US Patent 7,746,128, 2010 | 5 | 2010 |
| A programmable On-chip reference oscillator With slow-wave coplanar waveguide in 14-nm FinFET CMOS J Hwang, SH Chu, GS Jeong, Y Youn, W Kim, T Kim, DK Jeong IEEE Transactions on Circuits and Systems II: Express Briefs 67 (10), 1834-1838, 2019 | 4 | 2019 |
| Clock jitter measurement circuit and semiconductor device including the same KY Choo, H Kim, TI Kim, JH Kim, WS Kim US Patent 9,989,588, 2018 | 4 | 2018 |
| Edge detectors and systems of analyzing signal characteristics including the same DS Lee, WS Kim, JJ Park, DY Chung US Patent 9,893,721, 2018 | 4 | 2018 |
Minyoung SongDGIST (Daegu Gyeongbuk Institute of Science and Technology)在 dgist.ac.kr 的电子邮件经过验证
Minyoung SongDGIST (Daegu Gyeongbuk Institute of Science and Technology)在 dgist.ac.kr 的电子邮件经过验证
Deog-Kyoon JeongSeoul National University, Department of Electrical and Computer Engineering在 snu.ac.kr 的电子邮件经过验证