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Waleed El-Halwagy
Waleed El-Halwagy
在 ualberta.ca 的电子邮件经过验证
标题
引用次数
引用次数
年份
Investigation of wideband substrate-integrated vertically-polarized electric dipole antenna and arrays for mm-wave 5G mobile devices
W El-Halwagy, R Mirzavand, J Melzer, M Hossain, P Mousavi
IEEE Access 6, 2145-2157, 2017
992017
A 28-GHz quadrature fractional-N frequency synthesizer for 5G transceivers with less than 100-fs jitter based on cascaded PLL architecture
W El-Halwagy, A Nag, P Hisayasu, F Aryanfar, P Mousavi, M Hossain
IEEE Transactions on Microwave Theory and Techniques 65 (2), 396-413, 2017
882017
A 28GHz quadrature fractional-N synthesizer for 5G mobile communication with less than 100fs jitter in 65nm CMOS
W El-Halwagy, A Nag, P Hisayasu, F Aryanfar, P Mousavi, M Hossain
2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 118-121, 2016
252016
A 79dB SNDR, 10MHz BW, 675MS/s open-loop time-based ADC employing a 1.15 ps SAR-TDC
W El-Halwagy, P Mousavi, M Hossain
2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 321-324, 2016
152016
A programmable 8-bit, 10MHz BW, 6.8 mW, 200MSample/sec, 70dB SNDR VCO-based ADC using SC feedback for VCO linearization
W El-Halwagy, M Dessouky, H El-Ghitani
2013 IEEE 20th International Conference on Electronics, Circuits, and …, 2013
152013
A 100-MS/s–5-GS/s, 13–5-bit nyquist-rate reconfigurable time-domain ADC
W El-Halwagy, P Mousavi, M Hossain
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (10 …, 2018
132018
Fractional-N DPLL-based low-power clocking architecture for 1–14 Gb/s multi-standard transmitter
M Hossain, W El-Halwagy, AKMD Hossain
IEEE Journal of Solid-State Circuits 52 (10), 2647-2662, 2017
92017
A 28 GHz compact vertically-polarized dipole for 5G smartphone edge
W El-Halwagy, J Mezler, M Hossain, P Mousavi
2017 IEEE International Symposium on Antennas and Propagation & USNC/URSI …, 2017
72017
Analysis and design of analog-based voltage controlled oscillator linearization technique
W El-Halwagy, M Dessouky, H El-Ghitani
2013 8th IEEE Design and Test Symposium, 1-6, 2013
72013
Fence shaping of substrate integrated fan-beam electric dipole for high-band 5G
W El-Halwagy, R Mirzavand, J Melzer, M Hossain, P Mousavi
Electronics 8 (5), 545, 2019
62019
A substrate-integrated fan-beam dipole antenna with varied fence shape for mm-wave 5G wireless
W El-Halwagy, R Mirzavand, J Melzer, M Hossain, P Mousavi
2018 IEEE International Symposium on Antennas and Propagation & USNC/URSI …, 2018
62018
Circuits, Architectures and Antenna Design for 5G Wireless Transceivers
WM El-Halwagy
22018
A programmable 8.3 mW, 0.5–100MHz BW, 88.3–48.1 dB SNDR VCO-based ADC with switched capacitor linearization
W El-Halwagy, M Dessouky, H El-Ghitani
2013 IEEE International Conference of Electron Devices and Solid-state …, 2013
12013
Single and dual edge triggered phase error detection
W Roberts, Y Fouzar, W El-halwagy, K Kshonze
US Patent App. 18/465,898, 2024
2024
Determining a locked status of a clock tracking circuit
W Roberts, W El-halwagy, Y Fouzar, K Kshonze
US Patent App. 18/465,887, 2024
2024
Reduce dco frequency overlap-induced limit cycle in hybrid and digital plls
Y Fouzar, W El-halwagy, W Roberts, K Kshonze, F Warsalee
US Patent App. 18/448,783, 2024
2024
Triggering an error detector on rising and falling edges of clock signals, and generating an error signal therefrom
Y Fouzar, W El-halwagy, W Roberts, K Kshonze, F Warsalee
US Patent App. 18/333,827, 2024
2024
Reducing duty cycle mismatch of clocks for clock tracking circuits
W El-halwagy, Y Fouzar, K Kshonze, W Roberts, F Warsalee
US Patent App. 18/167,722, 2024
2024
Reducing duty cycle mismatch of clock signals for clock tracking circuits
W El-halwagy, Y Fouzar, K Kshonze, W Roberts, F Warsalee
US Patent App. 18/167,716, 2024
2024
Clock tracking circuit with digital integral path to provide control signals for digital and analog integral inputs of an oscillator
W El-halwagy, W Roberts, M Aliahmad
US Patent App. 17/823,418, 2023
2023
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