| Designing reliable systems from unreliable components: the challenges of transistor variability and degradation S Borkar Ieee Micro 25 (6), 10-16, 2005 | 2026 | 2005 |
| Parameter variations and impact on circuits and microarchitecture S Borkar, T Karnik, S Narendra, J Tschanz, A Keshavarzi, V De Proceedings of the 40th annual Design Automation Conference, 338-342, 2003 | 1906 | 2003 |
| Design challenges of technology scaling S Borkar IEEE micro 19 (4), 23-29, 1999 | 1694 | 1999 |
| Thousand core chips: a technology perspective S Borkar Proceedings of the 44th annual design automation conference, 746-749, 2007 | 1573 | 2007 |
| Exascale computing study: Technology challenges in achieving exascale systems K Bergman, S Borkar, D Campbell, W Carlson, W Dally, M Denneau, ... Defense Advanced Research Projects Agency Information Processing Techniques …, 2008 | 1550 | 2008 |
| The future of microprocessors S Borkar, AA Chien Communications of the ACM 54 (5), 67-77, 2011 | 1235 | 2011 |
| An 80-tile sub-100-w teraflops processor in 65-nm cmos SR Vangal, J Howard, G Ruhl, S Dighe, H Wilson, J Tschanz, D Finan, ... IEEE Journal of solid-state circuits 43 (1), 29-41, 2008 | 912 | 2008 |
| A 5-GHz mesh interconnect for a teraflops processor Y Hoskote, S Vangal, A Singh, N Borkar, S Borkar IEEE micro 27 (5), 51-61, 2007 | 883 | 2007 |
| A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS J Howard, S Dighe, Y Hoskote, S Vangal, D Finan, G Ruhl, D Jenkins, ... 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 108-109, 2010 | 859 | 2010 |
| Area-efficient linear regulator with ultra-fast load regulation P Hazucha, T Karnik, BA Bloechel, C Parsons, D Finan, S Borkar IEEE Journal of solid-state circuits 40 (4), 933-940, 2005 | 717 | 2005 |
| Warp: an integrated solution of high-speed parallel computing S Borkar, R Cohn, G Cox, S Gleason, T Gross, HT Kung, M Lam, B Moore, ... Conference on High Performance Networking and Computing: Proceedings of the …, 1988 | 529 | 1988 |
| A 48-core IA-32 processor in 45 nm CMOS using on-die message-passing and DVFS for performance and power scaling J Howard, S Dighe, SR Vangal, G Ruhl, N Borkar, S Jain, V Erraguntla, ... IEEE Journal of Solid-State Circuits 46 (1), 173-183, 2010 | 523 | 2010 |
| Technology and design challenges for low power and high performance V De, S Borkar Proceedings of the 1999 international symposium on Low power electronics and …, 1999 | 503 | 1999 |
| Scaling of stack effect and its application for leakage reduction S Narendra, V De, D Antoniadis, A Chandrakasan, S Borkar Proceedings of the 2001 international symposium on Low power electronics and …, 2001 | 471 | 2001 |
| A new technique for standby leakage reduction in high-performance circuits Y Ye, S Borkar, V De 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No …, 1998 | 440 | 1998 |
| A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package P Hazucha, G Schrom, J Hahn, BA Bloechel, P Hack, GE Dermer, ... IEEE Journal of Solid-State Circuits 40 (4), 838-845, 2005 | 413 | 2005 |
| Dynamic sleep transistor and body bias for active leakage power control of microprocessors JW Tschanz, SG Narendra, Y Ye, BA Bloechel, S Borkar, V De IEEE Journal of Solid-State Circuits 38 (11), 1838-1845, 2003 | 397 | 2003 |
| Review of on-chip inductor structures with magnetic films DS Gardner, G Schrom, F Paillet, B Jamieson, T Karnik, S Borkar IEEE Transactions on Magnetics 45 (10), 4760-4766, 2009 | 376 | 2009 |
| The 48-core SCC processor: the programmer's view TG Mattson, RF Van der Wijngaart, M Riepen, T Lehnig, P Brett, W Haas, ... SC'10: Proceedings of the 2010 ACM/IEEE International Conference for High …, 2010 | 361 | 2010 |
| Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors J Tschanz, S Narendra, Z Chen, S Borkar, M Sachdev, V De Proceedings of the 2001 international symposium on Low power electronics and …, 2001 | 348 | 2001 |
