| A dielectric-modulated tunnel-FET-based biosensor for label-free detection: Analytical modeling study and sensitivity analysis R Narang, KVS Reddy, M Saxena, RS Gupta, M Gupta IEEE transactions on electron devices 59 (10), 2809-2817, 2012 | 222 | 2012 |
| Comparative analysis of dielectric-modulated FET and TFET-based biosensor R Narang, M Saxena, M Gupta IEEE Transactions on Nanotechnology 14 (3), 427-435, 2015 | 211 | 2015 |
| Dielectric modulated tunnel field-effect transistor—A biomolecule sensor R Narang, M Saxena, RS Gupta, M Gupta IEEE electron device letters 33 (2), 266-268, 2011 | 156 | 2011 |
| Assessment of ambipolar behavior of a tunnel FET and influence of structural modifications R Narang, M Saxena, RS Gupta, M Gupta JSTS: Journal of Semiconductor Technology and Science 12 (4), 482-491, 2012 | 105 | 2012 |
| Impact of Temperature variations on the Device and Circuit Performance of Tunnel FET: A Simulation Study R Narang, M Saxena, RS Gupta, M Gupta IEEE Transactions on Nanotechnology 12 (6), 951-957, 0 | 96* | |
| Investigation of dielectric modulated (DM) double gate (DG) junctionless MOSFETs for application as a biosensors R Narang, M Saxena, M Gupta Superlattices and Microstructures 85, 557-572, 2015 | 95 | 2015 |
| Modeling and simulation investigation of sensitivity of symmetric split gate junctionless FET for biosensing application R Narang, M Saxena, M Gupta IEEE Sensors Journal 17 (15), 4853-4861, 2017 | 75 | 2017 |
| Analytical model of pH sensing characteristics of junctionless silicon on insulator ISFET R Narang, M Saxena, M Gupta IEEE Transactions on Electron Devices 64 (4), 1742-1750, 2017 | 71 | 2017 |
| Drain current model for a gate all around (GAA) p–n–p–n tunnel FET R Narang, M Saxena, RS Gupta, M Gupta Microelectronics Journal 44 (6), 479-488, 2013 | 58 | 2013 |
| Device and circuit level performance comparison of tunnel FET architectures and impact of heterogeneous gate dielectric R Narang, M Saxena, RS Gupta, M Gupta JSTS: Journal of Semiconductor Technology and Science 13 (3), 224-236, 2013 | 48 | 2013 |
| Modeling and TCAD assessment for gate material and gate dielectric engineered TFET architectures: circuit-level investigation for digital applications R Narang, M Saxena, M Gupta IEEE Transactions on Electron Devices 62 (10), 3348-3356, 2015 | 45 | 2015 |
| Modeling of gate underlap junctionless double gate MOSFET as bio-sensor R Narang, M Saxena, M Gupta Materials Science in Semiconductor Processing 71, 240-251, 2017 | 37 | 2017 |
| Linearity and analog performance analysis of double gate tunnel FET: effect of temperature and gate stack R Narang, M Saxena, RS Gupta, M Gupta International Journal of VLSI Design & Communication Systems 2 (3), 185, 2011 | 33 | 2011 |
| Model of GaSb-InAs pin gate all around BioTunnel FET R Narang, M Saxena, M Gupta IEEE Sensors Journal 19 (7), 2605-2612, 2018 | 30 | 2018 |
| Drain current model of a four-gate dielectric modulated MOSFET for application as a biosensor R Narang, M Saxena, M Gupta IEEE Transactions on Electron Devices 62 (8), 2636-2644, 2015 | 29 | 2015 |
| Modeling and simulation of junctionless double gate radiation sensitive FET (RADFET) dosimeter A Dubey, A Singh, R Narang, M Saxena, M Gupta IEEE Transactions on Nanotechnology 17 (1), 49-55, 2017 | 25 | 2017 |
| Simulation study for dual material gate hetero-dielectric TFET: Static performance analysis for analog applications R Narang, M Gupta, M Saxena 2013 Annual IEEE India Conference (INDICON), 1-6, 2013 | 22 | 2013 |
| Exploring the applicability of well optimized dielectric pocket tunnel transistor for future low power applications R Narang, M Saxena, M Gupta Superlattices and Microstructures 126, 8-16, 2019 | 20 | 2019 |
| Investigation of total ionizing dose effect on SOI tunnel FET A Dubey, R Narang, M Saxena, M Gupta Superlattices and Microstructures 133, 106186, 2019 | 18 | 2019 |
| Analysis of GaSb-InAs gate all around (GAA) pin tunnel FET (TFET) for application as a bio-sensor M Gupta, R Narang, M Saxena 2016 IEEE International nanoelectronics conference (INEC), 1-2, 2016 | 17 | 2016 |
Avashesh DubeyReliability Engineer at Pragmatic Semiconductor在 ieee.org 的电子邮件经过验证
