| Highly integrated scalable, flexible DSP megamodule architecture TD Anderson, J Zbiciak, DQ Bui, AA Chachad, K Chirca, N Bhoria, ... US Patent 9,606,803, 2017 | 117 | 2017 |
| Requester based transaction status reporting in a system with multi-level memory R Damodaran, AA Chachad, R Venkatasubramanian, ... US Patent 8,732,416, 2014 | 27 | 2014 |
| Highly integrated scalable, flexible DSP megamodule architecture TD Anderson, J Zbiciak, DQ Bui, AA Chachad, K Chirca, N Bhoria, ... US Patent 10,162,641, 2018 | 25 | 2018 |
| A 1.25 ghz 0.8 w c66x dsp core in 40nm cmos R Damodaran, T Anderson, S Agarwala, R Venkatasubramanian, M Gill, ... 2012 25th International Conference on VLSI Design, 286-291, 2012 | 25 | 2012 |
| Interleaved Memory Access from Multiple Requesters R Damodaran, N Bhoria US Patent App. 13/239,065, 2012 | 23 | 2012 |
| Dynamic management of write-miss buffer to reduce write-miss traffic N Bhoria, JRM Zbiciak, R Damodaran, AA Chachad US Patent App. 13/973,306, 2015 | 22 | 2015 |
| Zero cycle clock invalidate operation N Bhoria, R Damodaran, AA Chachad US Patent 9,244,837, 2016 | 11 | 2016 |
| Methods and apparatus for allocation in a victim cache system N Bhoria, TD Anderson, PM Hippleheuser US Patent 11,461,236, 2022 | 10 | 2022 |
| Integrated electro-optic hybrid communication system I Gerszberg, JA Okoro US Patent 7,336,902, 2008 | 8 | 2008 |
| Parallel processing of multiple block coherence operations N Bhoria, R Damodaran US Patent 8,977,821, 2015 | 7 | 2015 |
| Look up table with data element promotion D Bui, D Balasubramanian, N Bhoria, S Krishna US Patent 10,761,850, 2020 | 6 | 2020 |
| Victim cache with write miss merging N Bhoria, TD Anderson, P Hippleheuser US Patent 11,347,649, 2022 | 5 | 2022 |
| Highly integrated scalable, flexible DSP megamodule architecture TD Anderson, J Zbiciak, DQ Bui, A Chachad, K Chirca, N Bhoria, ... US Patent 11,036,648, 2021 | 5 | 2021 |
| Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors TD Anderson, J Zbiciak, AA Chachad, K Chirca, N Bhoria, DM Thompson, ... US Patent 9,557,936, 2017 | 5 | 2017 |
| Aliased mode for cache controller AA Chachad, TD Anderson, PK Swami, N Bhoria, DM Thompson, ... US Patent 11,392,498, 2022 | 4 | 2022 |
| Methods and apparatus to facilitate read-modify-write support in a victim cache N Bhoria, TD Anderson, PM Hippleheuser US Patent 11,640,357, 2023 | 3 | 2023 |
| Global coherence operations AA Chachad, N Bhoria, DM Thompson, N Muralidharan US Patent 11,294,707, 2022 | 3 | 2022 |
| Look-up table initialize N Bhoria, DB Samudrala, D Bui, R Venkatasubramanian US Patent 11,226,822, 2022 | 3 | 2022 |
| Methods and apparatus to facilitate atomic compare and swap in cache for a coherent level 1 data cache system N Bhoria, TD Anderson, PM Hippleheuser US Patent 11,119,935, 2021 | 3 | 2021 |
| Memory attribute sharing between differing cache levels of multilevel cache R Damodaran, JRM Zbiciak, N Bhoria US Patent 9,183,084, 2015 | 3 | 2015 |
