| Design of high-speed low-power 3-2 counter and 4-2 compressor for fast multipliers SF Hsiao, MR Jiang, JS Yeh Electronics Letters 34 (4), 341-342, 1998 | 173 | 1998 |
| Para-CORDIC: Parallel CORDIC rotation algorithm TB Juang, SF Hsiao, MY Tsai IEEE Transactions on Circuits and Systems I: Regular Papers 51 (8), 1515-1524, 2004 | 158 | 2004 |
| Design and application of faithfully rounded and truncated multipliers with combined deletion, reduction, truncation, and rounding HJ Ko, SF Hsiao IEEE Transactions on Circuits and Systems II: Express Briefs 58 (5), 304-308, 2011 | 106 | 2011 |
| Householder CORDIC algorithms SF Hsiao, JM Delosme IEEE Transactions on Computers 44 (8), 990-1001, 1995 | 95 | 1995 |
| Low-error carry-free fixed-width multipliers with low-cost compensation circuits TB Juang, SF Hsiao IEEE Transactions on Circuits and Systems II: Express Briefs 52 (6), 299-303, 2005 | 92 | 2005 |
| Low-cost FIR filter designs based on faithfully rounded truncated multiple constant multiplication/accumulation SF Hsiao, JHZ Jian, MC Chen IEEE Transactions on Circuits and Systems II: Express Briefs 60 (5), 287-291, 2013 | 86 | 2013 |
| Parallel singular value decomposition of complex matrices using multidimensional CORDIC algorithms SF Hsiao, JM Delosme IEEE Transactions on signal processing 44 (3), 685-697, 1996 | 81 | 1996 |
| Memory-free low-cost designs of advanced encryption standard using common subexpression elimination for subfunctions in transformations SF Hsiao, MC Chen, CS Tu IEEE Transactions on Circuits and Systems I: Regular Papers 53 (3), 615-626, 2006 | 80 | 2006 |
| A memory-efficient and high-speed sine/cosine generator based on parallel CORDIC rotations SF Hsiao, YH Hu, TB Juang IEEE Signal Processing Letters 11 (2), 152-155, 2004 | 53 | 2004 |
| VLSI design of an efficient embedded zerotree wavelet coder with function of digital watermarking SF Hsiao, YC Tai, KH Chang IEEE Transactions on Consumer Electronics 46 (3), 628-636, 2000 | 43 | 2000 |
| Efficient VLSI implementations of fast multiplierless approximated DCT using parameterized hardware modules for silicon intellectual property design SF Hsiao, YH Hu, TB Juang, CH Lee IEEE Transactions on Circuits and Systems I: Regular Papers 52 (8), 1568-1579, 2005 | 42 | 2005 |
| Hierarchical multipartite function evaluation SF Hsiao, CS Wen, YH Chen, KC Huang IEEE Transactions on Computers 66 (1), 89-99, 2016 | 29 | 2016 |
| Table size reduction methods for faithfully rounded lookup-table-based multiplierless function evaluation SF Hsiao, PH Wu, CS Wen, PK Meher IEEE Transactions on Circuits and Systems II: Express Briefs 62 (5), 466-470, 2014 | 26 | 2014 |
| High‐performance Multiplexer‐based Logic Synthesis Using Pass‐transistor Logic SF Hsiao, JS Yeh, DY Chen VLSI Design 15 (1), 417-426, 2002 | 25 | 2002 |
| Redundant constant-factor implementation of multi-dimensional CORDIC and its application to complex SVD SF Hsiao, CY Lau, JM Delosme Journal of VLSI signal processing systems for signal, image and video …, 2000 | 25 | 2000 |
| New matrix formulation for two-dimensional DCT/IDCT computation and its distributed-memory VLSI implementation SF Hsiao, JM Tseng IEE Proceedings-Vision, Image and Signal Processing 149 (2), 97-107, 2002 | 24 | 2002 |
| Efficient substructure sharing methods for optimising the inner-product operations in Rijndael advanced encryption standard SF Hsiao, MC Chen IEE Proceedings-Computers and Digital Techniques 152 (5), 653-665, 2005 | 23 | 2005 |
| The CORDIC householder algorithm SF Hsiao, JM Delosme Proceedings 10th IEEE Symposium on Computer Arithmetic, 256,257,258,259,260 …, 1991 | 23 | 1991 |
| A new hardware-efficient algorithm and architecture for computation of 2-D DCTs on a linear array SF Hsiao, WR Shiue IEEE Transactions on Circuits and Systems for Video Technology 11 (11), 1149 …, 2001 | 22 | 2001 |
| Design and implementation of a novel linear-array DCT/IDCT processor with complexity of order log2 N SF Hsiao, WR Shiue, JM Tseng IEE Proceedings-Vision, Image and Signal Processing 147 (5), 400-408, 2000 | 22 | 2000 |
