Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits K Roy, S Mukhopadhyay, H Mahmoodi-Meimand Proceedings of the IEEE 91 (2), 305-327, 2003 | 3151 | 2003 |
Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates Q Cao, H Kim, N Pimparkar, JP Kulkarni, C Wang, M Shim, K Roy, ... Nature 454 (7203), 495-500, 2008 | 1388 | 2008 |
Towards spike-based machine intelligence with neuromorphic computing K Roy, A Jaiswal, P Panda Nature 575 (7784), 607-617, 2019 | 1366 | 2019 |
Gated-Vdd a circuit technique to reduce leakage in deep-submicron cache memories M Powell, SH Yang, B Falsafi, K Roy, TN Vijaykumar Proceedings of the 2000 international symposium on Low power electronics and …, 2000 | 1140 | 2000 |
Going deeper in spiking neural networks: VGG and residual architectures A Sengupta, Y Ye, R Wang, C Liu, K Roy Frontiers in neuroscience 13, 95, 2019 | 1040 | 2019 |
Low-power CMOS VLSI circuit design K Roy, SC Prasad John Wiley & Sons, 2009 | 971 | 2009 |
Low-power digital signal processing using approximate adders V Gupta, D Mohapatra, A Raghunathan, K Roy IEEE transactions on computer-aided design of integrated circuits and …, 2012 | 911 | 2012 |
A 32 kb 10T sub-threshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS IJ Chang, JJ Kim, SP Park, K Roy IEEE Journal of Solid-State Circuits 44 (2), 650-658, 2009 | 664 | 2009 |
Analysis and characterization of inherent application resilience for approximate computing VK Chippa, ST Chakradhar, K Roy, A Raghunathan Proceedings of the 50th Annual Design Automation Conference, 1-9, 2013 | 643 | 2013 |
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS S Mukhopadhyay, H Mahmoodi, K Roy IEEE transactions on computer-aided design of integrated circuits and …, 2005 | 605 | 2005 |
IMPACT: IMPrecise adders for low-power approximate computing V Gupta, D Mohapatra, SP Park, A Raghunathan, K Roy IEEE/ACM International Symposium on Low Power Electronics and Design, 409-414, 2011 | 598 | 2011 |
A 160 mV robust Schmitt trigger based subthreshold SRAM JP Kulkarni, K Kim, K Roy IEEE Journal of Solid-State Circuits 42 (10), 2303-2313, 2007 | 593 | 2007 |
Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks Z Chen, M Johnson, L Wei, K Roy Proceedings of the 1998 international symposium on Low power electronics and …, 1998 | 512 | 1998 |
PUMA: A programmable ultra-efficient memristor-based accelerator for machine learning inference A Ankit, IE Hajj, SR Chalamalasetti, G Ndu, M Foltin, RS Williams, ... Proceedings of the twenty-fourth international conference on architectural …, 2019 | 430 | 2019 |
Design and optimization of dual-threshold circuits for low-voltage low-power applications L Wei, Z Chen, K Roy, MC Johnson, Y Ye, VK De IEEE Transactions on Very Large Scale Integration (VLSI) Systems 7 (1), 16-24, 1999 | 409 | 1999 |
SALSA: Systematic logic synthesis of approximate circuits S Venkataramani, A Sabne, V Kozhikkottu, K Roy, A Raghunathan Proceedings of the 49th Annual Design Automation Conference, 796-801, 2012 | 405 | 2012 |
Enabling spike-based backpropagation for training deep neural network architectures C Lee, SS Sarwar, P Panda, G Srinivasan, K Roy Frontiers in neuroscience 14, 497482, 2020 | 400 | 2020 |
Leakage control with efficient use of transistor stacks in single threshold CMOS MC Johnson, D Somasekhar, K Roy Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 442-445, 1999 | 393 | 1999 |
Sense-amp based adder with source follower evaluation tree JJ Kim, CTK Chuang, RV Joshi, K Roy US Patent 6,789,099, 2004 | 385 | 2004 |
Robust subthreshold logic for ultra-low power operation H Soeleman, K Roy, BC Paul IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (1), 90-99, 2001 | 377 | 2001 |