| An open-source framework for autonomous SoC design with analog block generation T Ajayi, S Kamineni, YK Cherivirala, M Fayazi, K Kwon, M Saligane, ... 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration …, 2020 | 29 | 2020 |
| A power-efficient brain-machine interface system with a sub-mW feature extraction and decoding ASIC demonstrated in nonhuman primates H An, SR Nason-Tomaszewski, J Lim, K Kwon, MS Willsey, PG Patil, ... IEEE transactions on biomedical circuits and systems 16 (3), 395-408, 2022 | 14 | 2022 |
| Fully-autonomous SoC synthesis using customizable cell-based synthesizable analog circuits R Dreslinski, D Wentzloff, M Fayazi, K Kwon, D Blaauw, D Sylvester, ... University of Michigan Ann Arbor United States, Tech. Rep, 2019 | 10 | 2019 |
| PLL fractional spur’s impact on FSK spectrum and a synthesizable ADPLL for a Bluetooth transmitter K Kwon, OAB Abdelatty, DD Wentzloff IEEE Journal of Solid-State Circuits 58 (5), 1271-1284, 2023 | 7 | 2023 |
| Open-Source Fully-Synthesizable ADPLL for a Bluetooth Low-Energy Transmitter in 12nm FinFET Technology K Kwon, O Abdelatty, D Wentzloff 2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 155-158, 2022 | 7 | 2022 |
| An 81.6 dB SNDR 15.625 MHz BW third-order CT SDM with a true time-interleaving noise-shaping quantizer S Lee, T Kang, S Song, K Kwon, MP Flynn IEEE Journal of Solid-State Circuits 58 (4), 929-938, 2022 | 4 | 2022 |
| Fully autonomous mixed signal SoC design & layout generation platform T Ajayi, Y Cherivirala, K Kwon, S Kamineni, M Saligane, M Fayazi, ... IEEE, 2020 | 4 | 2020 |
| An 81.6dB SNDR 15.625MHz BW 3rd Order CT SDM with a True TI NS Quantizer S Lee, T Kang, S Song, K Kwon, M Flynn 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 3 | 2022 |
| Synthesizable ADPLL Generator: From Specification to GDS K Kwon, DD Wentzloff 2023 19th International Conference on Synthesis, Modeling, Analysis and …, 2023 | 2 | 2023 |
| Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation T Ajayi, S Kamineni, M Fayazi, YK Cherivirala, K Kwon, S Gupta, W Duan, ... VLSI-SoC: Design Trends: 28th IFIP WG 10.5/IEEE International Conference on …, 2021 | 1 | 2021 |
| Automated Design Flow for Synthesizable ADPLL: From Specification to GDS K Kwon, DD Wentzloff AEU-International Journal of Electronics and Communications, 155204, 2024 | | 2024 |
| A 800 MHz Fully Synthesizable PLL with Calibration-Free Feedforward Noise Cancellation K Kwon, DD Wentzloff 2023 Joint Conference of the European Frequency and Time Forum and IEEE …, 2023 | | 2023 |
| Circuits and Techniques for All-Digital Frequency Synthesizers and Design Automation K Kwon | | 2023 |
