| A 16-mW 78-dB SNDR 10-MHz BW CTADC Using Residue-Cancelling VCO-Based Quantizer K Reddy, S Rao, R Inti, B Young, A Elshazly, M Talegaonkar, ... IEEE journal of solid-state circuits 47 (12), 2916-2927, 2012 | 228 | 2012 |
| Clock multiplication techniques using digital multiplying delay-locked loops A Elshazly, R Inti, B Young, PK Hanumolu IEEE Journal of Solid-State Circuits 48 (6), 1416-1428, 2013 | 120 | 2013 |
| A 0.5-to-2.5 Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance R Inti, W Yin, A Elshazly, N Sasidhar, PK Hanumolu IEEE Journal of Solid-State Circuits 46 (12), 3150-3162, 2011 | 117 | 2011 |
| A 0.7-to-3.5 GHz 0.6-to-2.8 mW highly digital phase-locked loop with bandwidth tracking W Yin, R Inti, A Elshazly, B Young, PK Hanumolu IEEE Journal of Solid-State Circuits 46 (8), 1870-1880, 2011 | 86 | 2011 |
| A 4–32 Gb/s bidirectional link with 3-tap FFE/6-tap DFE and collaborative CDR in 22 nm CMOS T Musah, JE Jaussi, G Balamurugan, S Hyvonen, TC Hsueh, G Keskin, ... IEEE Journal of Solid-State Circuits 49 (12), 3079-3090, 2014 | 66 | 2014 |
| A reference-less clock and data recovery circuit using phase-rotating phase-locked loop G Shu, S Saxena, WS Choi, M Talegaonkar, R Inti, A Elshazly, B Young, ... IEEE Journal of Solid-State Circuits 49 (4), 1036-1047, 2014 | 63 | 2014 |
| A 0.4-to-3 GHz digital PLL with PVT insensitive supply noise cancellation using deterministic background calibration A Elshazly, R Inti, W Yin, B Young, PK Hanumolu IEEE journal of solid-state circuits 46 (12), 2759-2771, 2011 | 47 | 2011 |
| A 3.1 mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS T Toifl, M Ruegg, R Inti, C Menolfi, M Brändli, M Kossel, P Buchmann, ... 2012 Symposium on VLSI Circuits (VLSIC), 102-103, 2012 | 42 | 2012 |
| A highly digital 0.5-to-4Gb/s 1.9 mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS R Inti, A Elshazly, B Young, W Yin, M Kossel, T Toifl, PK Hanumolu 2011 IEEE International Solid-State Circuits Conference, 152-154, 2011 | 41 | 2011 |
| 26.4 A 25.6 Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS TC Hsueh, G Balamurugan, J Jaussi, S Hyvonen, J Kennedy, G Keskin, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 39 | 2014 |
| A TDC-less 7 mW 2.5 Gb/s digital CDR with linear loop dynamics and offset-free data recovery W Yin, R Inti, A Elshazly, M Talegaonkar, B Young, PK Hanumolu IEEE journal of solid-state circuits 46 (12), 3163-3173, 2011 | 37 | 2011 |
| A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration A Elshazly, R Inti, W Yin, B Young, PK Hanumolu 2011 IEEE International Solid-State Circuits Conference, 92-94, 2011 | 35 | 2011 |
| A 1.5GHz 890μW digital MDLL with 400fsrmsintegrated jitter, −55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC A Elshazly, R Inti, B Young, PK Hanumolu 2012 IEEE International Solid-State Circuits Conference, 242-244, 2012 | 33 | 2012 |
| Digital clock and data recovery circuit design: Challenges and tradeoffs M Talegaonkar, R Inti, PK Hanumolu 2011 IEEE Custom Integrated Circuits Conference (CICC), 1-8, 2011 | 32 | 2011 |
| 26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS J Jaussi, G Balamurugan, S Hyvonen, TC Hsueh, T Musah, G Keskin, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 31 | 2014 |
| A 900mA 93% efficient 50µA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage-and current-mode control Q Khan, A Elshazly, S Rao, R Inti, PK Hanumolu 2012 symposium on VLSI circuits (VLSIC), 182-183, 2012 | 24 | 2012 |
| A 1.6 mW 1.6 ps-rms-Jitter 2.5 GHz digital PLL with 0.7-to-3.5 GHz frequency range in 90nm CMOS W Yin, R Inti, PK Hanumolu IEEE Custom Integrated Circuits Conference 2010, 1-4, 2010 | 20 | 2010 |
| A scalable 32–56 Gb/s 0.56–1.28 pJ/b voltage-mode VCSEL-based optical transmitter in 28-nm CMOS M Mansuri, R Inti, J Kennedy, J Qiu, CM Hsu, J Sharma, H Li, B Casper, ... IEEE Journal of Solid-State Circuits 57 (3), 757-766, 2021 | 13 | 2021 |
| A 1.2–5Gb/s 1.4–2pJ/b serial link in 22nm CMOS with a direct data-sequencing blind oversampling CDR S Shekhar, R Inti, J Jaussi, TC Hsueh, B Casper 2015 Symposium on VLSI Circuits (VLSI Circuits), C350-C351, 2015 | 12 | 2015 |
| A 1.5 GHz 1.35 mW− 112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity A Elshazly, R Inti, M Talegaonkar, PK Hanumolu 2012 Symposium on VLSI Circuits (VLSIC), 188-189, 2012 | 12 | 2012 |
Amr ElshazlyIntel corporation / Oregon State University在 ieee.org 的电子邮件经过验证
