| A 40–550 MHz harmonic-free all-digital delay-locked loop using a variable SAR algorithm RJ Yang, SI Liu IEEE Journal of solid-state circuits 42 (2), 361-373, 2007 | 192 | 2007 |
| A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 CMOS Technology RJ Yang, SI Liu IEEE Journal of Solid-State Circuits 42 (11), 2338-2347, 2007 | 100 | 2007 |
| A 155.52 Mbps-3.125 Gbps continuous-rate clock and data recovery circuit RJ Yang, KH Chao, SC Hwu, CK Liang, SI Liu IEEE Journal of solid-state circuits 41 (6), 1380-1390, 2006 | 79 | 2006 |
| A 3.125-Gb/s clock and data recovery circuit for the 10-Gbase-LX4 Ethernet RJ Yang, SP Chen, SI Liu IEEE Journal of Solid-State Circuits 39 (8), 1356-1360, 2004 | 70 | 2004 |
| An all-digital fast-locking programmable DLL-based clock generator CK Liang, RJ Yang, SI Liu IEEE Transactions on Circuits and Systems I: Regular Papers 55 (1), 361-369, 2008 | 44 | 2008 |
| Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection HH Chang, RJ Yang, SI Liu IEEE Transactions on Circuits and Systems I: Regular Papers 51 (12), 2356-2364, 2004 | 39 | 2004 |
| A 200-Mbps/spl sim/2-Gbps continuous-rate clock-and-data-recovery circuit RJ Yang, KH Chao, SI Liu IEEE Transactions on Circuits and Systems I: Regular Papers 53 (4), 842-847, 2006 | 35 | 2006 |
| Designing a SAR-based all-digital delay-locked loop with constant acquisition cycles using a resettable delay line CY Yao, YH Ho, YY Chiu, RJ Yang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (3), 567-574, 2014 | 34 | 2014 |
| A fast-transient wide-voltage-range digital-controlled buck converter with cycle-controlled DPWM WC Chen, CC Chen, CY Yao, RJ Yang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (1), 17-25, 2015 | 28 | 2015 |
| A wide-range multiphase delay-locked loop using mixed-mode VCDLs RJ Yang, SI Liu IEICE transactions on electronics 88 (6), 1248-1252, 2005 | 12 | 2005 |
| Loop latency reduction technique for all-digital clock and data recovery circuits IF Chen, RJ Yang, SI Liu 2009 IEEE Asian Solid-State Circuits Conference, 309-312, 2009 | 10 | 2009 |
| Analog circuit design for communication SOC SHL Tu, DL Shen, RJ Yang Bentham Science Publishers, 2012 | 5 | 2012 |
| A 1.25 Gbps all-digital clock and data recovery circuit with binary frequency acquisition CS Oulee, RJ Yang APCCAS 2008-2008 IEEE Asia Pacific Conference on Circuits and Systems, 680-683, 2008 | 5 | 2008 |
| A high isolation 0.15 μm depletion-mode pHEMT SPDT switch using field-plate technology CS Cheng, SW Lin, CC Wei, HC Chiu, RJ Yang 2007 Asia-Pacific Microwave Conference, 1-4, 2007 | 5 | 2007 |
| A wide-range all-digital delay-locked loop using fast-lock variable SAR algorithm WC Chen, RJ Yang, CY Yao, CC Chen 2012 International Symposium on Intelligent Signal Processing and …, 2012 | 4 | 2012 |
| RF performance of double heterojunction high electron mobility transistor with various lower/upper planar doping ratio designs on SPST switchs application HC Chiu, CW Chen, YC Huang, RJ Yang 2007 Asia-Pacific Microwave Conference, 1-4, 2007 | 3 | 2007 |
| A compact size Ka band pHEMT MMIC frequency tripler with CPW technology SW Lin, CS Cheng, CC Wei, HC Chiu, RJ Yang 2007 Asia-Pacific Microwave Conference, 1-3, 2007 | 3 | 2007 |
| A 1.7/spl sim/3.125 Gbps clock and data recovery circuit using a gated frequency detector RJ Yang, SI Liu Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System …, 2004 | 2 | 2004 |
| Delay-Locked Loop and Clock Data Recovery for Wired Communications RJ Yang Analog Circuit Design for Communication SOC, 108, 2012 | | 2012 |
| Ding-Lan Shen SHL Tu, RJ Yang Analog Circuit Design for Communication SOC, 2, 2012 | | 2012 |
Sy-Chyuan HwuUCLA and National Taiwan University在 g.ucla.edu 的电子邮件经过验证
Sy-Chyuan HwuUCLA and National Taiwan University在 g.ucla.edu 的电子邮件经过验证