A novel hardware architecture of the Lucas–Kanade optical flow for reduced frame memory access HS Seong, CE Rhee, HJ Lee IEEE transactions on circuits and systems for video technology 26 (6), 1187-1199, 2015 | 37 | 2015 |
Method of generating test clock signal and test clock signal generator for testing semiconductor devices HS Seong US Patent 7,810,003, 2010 | 19 | 2010 |
Graphics display systems with data compression and methods of performing data compression of graphics data HS Seong, SJ Cho US Patent 7,230,630, 2007 | 9 | 2007 |
Display apparatus and controlling method thereof MC Kim, HS Seong US Patent 10,779,030, 2020 | 6 | 2020 |
AVS3 decoder architecture and VLSI implementation for 8K UHDTV application K Joe, H Oh, S Jeon, HS Seong, C Jung 2022 IEEE International Conference on Consumer Electronics (ICCE), 1-2, 2022 | 5 | 2022 |
A VLSI design of real-time and scalable Lucas-Kanade optical flow HS Seong, HJ Lee 2014 International Conference on Electronics, Information and Communications …, 2014 | 5 | 2014 |
Image processing method and apparatus HS Seong, Y Kwon, KM Kim, Y Kim US Patent 10,325,347, 2019 | 1 | 2019 |
Optimized Hardware Architecture of Tile to Raster Scan Buffer for Video Decoder and Display Processor HS Seong, C Jung 2023 IEEE International Conference on Consumer Electronics (ICCE), 1-3, 2023 | | 2023 |
Assistant Cache design to minimize SoC System Bandwidth inefficiency caused by Partial Traffic of Legacy Reused IP H An, J Moon, J Park, HS Seong, C Jung 2023 IEEE International Conference on Consumer Electronics (ICCE), 1-3, 2023 | | 2023 |
Efficient Digital Television System Booting Method DK Lim, HS Seong, C Jung 2023 IEEE International Conference on Consumer Electronics (ICCE), 1-2, 2023 | | 2023 |