| Soft-error tolerance analysis and optimization of nanometer circuits YS Dhillon, AU Diril, A Chatterjee Design, Automation, and Test in Europe: The Most Influential Papers of 10 …, 2008 | 171 | 2008 |
| Analysis and optimization of nanometer CMOS circuits for soft-error tolerance YS Dhillon, AU Diril, A Chatterjee, AD Singh IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14 (5), 514-524, 2006 | 118 | 2006 |
| Algorithm for achieving minimum energy consumption in CMOS circuits using multiple supply and threshold voltages at the module level YS Dhillon, AU Diril, A Chatterjee, HHS Lee ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003 | 53 | 2003 |
| Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages AU Diril, YS Dhillon, A Chatterjee, AD Singh IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (9 …, 2005 | 42 | 2005 |
| Power estimation based on block activity H Cha, RJ Hasslen III, JA Robinson, SJ Treichler, AU Diril US Patent 8,060,765, 2011 | 30 | 2011 |
| Load and logic co-optimization for design of soft-error resistant nanometer CMOS circuits YS Dhillon, AU Diril, A Chatterjee, C Metra 11th IEEE International On-Line Testing Symposium, 35-40, 2005 | 28 | 2005 |
| Design of adaptive nanometer digital systems for effective control of soft error tolerance AU Diril, YS Dhillon, A Chatterjee, AD Singh 23rd IEEE VLSI Test Symposium (VTS'05), 298-303, 2005 | 25 | 2005 |
| Sizing CMOS circuits for increased transient error tolerance YS Dhillon, AU Diril, A Chatterjee, AD Singh Proceedings. 10th IEEE International On-Line Testing Symposium, 11-16, 2004 | 24 | 2004 |
| The elusive metric for low-power architecture research HHS Lee, JB Fryman, AU Diril, YS Dhillon Proceedings of the Workshop on Complexity-Effective Design, 2003 | 20 | 2003 |
| Adaptive design for performance-optimized robustness R Datta, JA Abraham, AU Diril, A Chatterjee, K Nowka 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2006 | 13 | 2006 |
| Probabilistic self-adaptation of nanoscale CMOS circuits: Yield maximization under increased intra-die variations M Ashouei, MM Nisar, A Chatterjee, AD Singh, AU Diril 20th International Conference on VLSI Design held jointly with 6th …, 2007 | 11 | 2007 |
| An o (n) supply voltage assignment algorithm for low-energy serially connected cmos modules and a heuristic extension to acyclic data flow graphs AU Diril, YS Dhillon, K Choi, A Chatterjee IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings., 173-179, 2003 | 7 | 2003 |
| Efficient tile-based rasterization AU Diril, F Garritsen US Patent 8,416,241, 2013 | 6 | 2013 |
| Low-power domino circuits using NMOS pull-up on off-critical paths AU Diril, YS Dhillon, A Chatterjee, AD Singh Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005 | 5 | 2005 |
| Low-power dual Vth pseudo dual Vdd domino circuits YS Dhillon, AU Diril, A Chatterjee, AD Singh Proceedings of the 17th symposium on Integrated Circuits and System Design …, 2004 | 4 | 2004 |
| Storage element with multiple clock circuits AU Diril, AT Moerschell, AP DeLaurier US Patent 9,761,303, 2017 | 3 | 2017 |
| Circuit level techniques for power and reliability optimization of CMOS logic AU Diril Georgia Institute of Technology, 2005 | 3 | 2005 |
| Serial pixel processing with storage for overlapping texel data TJ Bergland, AU Diril, AP DeLaurier US Patent 10,255,655, 2019 | 2 | 2019 |
| Processed texel cache J Wang, AU Diril US Patent 9,600,909, 2017 | 2 | 2017 |
| Global co-op: Engineering education through outsourcing O Ergin, AU Diril, WJ Dai 2012 2nd Interdisciplinary Engineering Design Education Conference (IEDEC …, 2012 | 1 | 2012 |
Oğuz ErginProfessor, TOBB ETÜ, Ankara, Türkiye在 etu.edu.tr 的电子邮件经过验证
Oğuz ErginProfessor, TOBB ETÜ, Ankara, Türkiye在 etu.edu.tr 的电子邮件经过验证