| A 0.85 fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS HY Tai, YS Hu, HW Chen, HS Chen 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 254 | 2014 |
| A 14-b 20-Msamples/s CMOS pipelined ADC HS Chen, BS Song, K Bacrania IEEE Journal of Solid-State Circuits 36 (6), 997-1001, 2001 | 101 | 2001 |
| Calibration of resistor ladder using difference measurement and parallel resistive correction HS Chen, K Bacrania, EC Sung, JM Hakkarainen, BS Song, BL Allen, ... US Patent 6,628,216, 2003 | 70 | 2003 |
| A 3.2 fJ/c.-s. 0.35 v 10b 100ks/s SAR ADC in 90nm cmos HY Tai, HW Chen, HS Chen 2012 Symposium on VLSI Circuits (VLSIC), 92-93, 2012 | 62 | 2012 |
| A High-Efficiency CMOS DC-DC Converter With 9-us Transient Recovery Time PJ Liu, WS Ye, JN Tai, HS Chen, JH Chen, YJE Chen IEEE Transactions on Circuits and Systems I: Regular Papers 59 (3), 575-583, 2012 | 48 | 2012 |
| A 2.4 GHz fully integrated cascode-cascade CMOS Doherty power amplifier LY Yang, HS Chen, YJE Chen IEEE Microwave and Wireless Components Letters 18 (3), 197-199, 2008 | 48 | 2008 |
| A 10-b 320-MS/s stage-gain-error self-calibration pipeline ADC CJ Tseng, HW Chen, WT Shen, WC Cheng, HS Chen IEEE Journal of Solid-State Circuits 47 (6), 1334-1343, 2012 | 40 | 2012 |
| Signal/power integrity modeling of high-speed memory modules using chip-package-board coanalysis HH Chuang, WD Guo, YH Lin, HS Chen, YC Lu, YS Cheng, MZ Hong, ... IEEE transactions on electromagnetic compatibility 52 (2), 381-391, 2010 | 39 | 2010 |
| System and method of DC calibration of amplifiers EC Sung, K Bacrania, HS Chen, JM Hakkarainen, BS Song, BL Allen, ... US Patent 6,714,886, 2004 | 35 | 2004 |
| A 1.5-V 10-ppm//spl deg/C 2nd-order curvature-compensated CMOS bandgap reference with trimming SW Hsiao, YC Huang, D Liang, HWK Chen, HS Chen 2006 IEEE International Symposium on Circuits and Systems (ISCAS), 4 pp.-568, 2006 | 32 | 2006 |
| Analog to digital converter using subranging and interpolation K Bacrania, HS Chen, EC Sung, BS Song, JM Hakkarainen, BL Allen, ... US Patent 6,570,523, 2003 | 32 | 2003 |
| A 14 b 20 MSample/s CMOS pipelined ADC HS Chen, K Bacrania, BS Song 2000 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2000 | 30 | 2000 |
| A 1-GS/s 6-Bit two-channel two-step ADC in 0.13-um CMOS HW Chen, IC Chen, HC Tseng, HS Chen IEEE Journal of Solid-State Circuits 44 (11), 3051-3059, 2009 | 29 | 2009 |
| A 6-bit 1-GS/s two-step SAR ADC in 40-nm CMOS HY Tai, CH Tsai, PY Tsai, HW Chen, HS Chen IEEE Transactions on Circuits and Systems II: Express Briefs 61 (5), 339-343, 2014 | 28 | 2014 |
| A 3mW 12b 10MS/s sub-range SAR ADC HW Chen, YH Liu, YH Lin, HS Chen 2009 IEEE Asian Solid-State Circuits Conference, 153-156, 2009 | 27 | 2009 |
| A 0.6 V 6.4 fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40nm CMOS YS Hu, CH Shih, HY Tai, HW Chen, HS Chen 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC), 81-84, 2014 | 26 | 2014 |
| Track and hold with dual pump circuit JM Hakkarainen, K Bacrania, EC Sung, HS Chen, BS Song, M Sanchez US Patent 6,731,155, 2004 | 26 | 2004 |
| An 8 b 700 MS/s 1 b/cycle SAR ADC using a delay-shift technique TH Tsai, HY Tai, PY Tsai, CH Tsai, HS Chen IEEE Transactions on Circuits and Systems I: Regular Papers 63 (5), 683-692, 2016 | 22 | 2016 |
| A 6-bit 1.6 GS/s Flash ADC in 0.18-μm CMOS with Reversed-Reference Dummy CK Hung, JF Shiu, IC Chen, HS Chen 2006 IEEE Asian Solid-State Circuits Conference, 335-338, 2006 | 22 | 2006 |
| Spur-reduction design of frequency-hopping DC–DC converters PJ Liu, JN Tai, HS Chen, JH Chen, YJE Chen IEEE transactions on power electronics 27 (11), 4763-4771, 2011 | 20 | 2011 |
