| A study on the programming structures for RRAM-based FPGA architectures X Tang, G Kim, PE Gaillardon, G De Micheli IEEE Transactions on Circuits and Systems I: Regular Papers 63 (4), 503-516, 2016 | 53 | 2016 |
| A 161-mW 56-Gb/s ADC-based discrete multitone wireline receiver data-path in 14-nm FinFET G Kim, L Kull, D Luu, M Braendli, C Menolfi, PA Francese, H Yueksel, ... IEEE Journal of Solid-State Circuits 55 (1), 38-48, 2019 | 43 | 2019 |
| A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells PE Gaillardon, X Tang, G Kim, G De Micheli Very Large Scale Integration (VLSI) Systems, 2015 | 43 | 2015 |
| Design Space Exploration of Single-Lane OFDM-Based Serial Links for High-Speed Wireline Communications G Kim IEEE Open Journal of Circuits and Systems 3, 134-146, 2022 | 7 | 2022 |
| 32.4 A 1V-Supply -Input-Range 1kHz-BW 181.9dB-FOMDR179.4dB-FOMSNDR 2nd-Order Noise-Shaping SAR-ADC with Enhanced Input Impedance in … G Kim, S Lee, T Seol, S Baik, Y Shin, G Kim, JH Yoon, AK George, J Lee 2023 IEEE International Solid-State Circuits Conference (ISSCC), 484-486, 2023 | 6 | 2023 |
| A 4.8 pJ/b 56Gb/s ADC-based PAM-4 wireline receiver data-path with cyclic prefix in 14nm FinFET G Kim, L Kull, D Luu, M Braendli, C Menolfi, PA Francese, H Yueksel, ... 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 239-240, 2019 | 6 | 2019 |
| Design considerations and performance trade-offs for 56Gb/s discrete multi-tone electrical link G Kim, W Kwon, T Toifl, Y Leblebici, HM Bae 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems …, 2019 | 5 | 2019 |
| Parallel implementation technique of digital equalizer for ultra-high-speed wireline receiver G Kim, L Kull, D Luu, M Braendli, C Menolfi, PA Francese, C Aprile, T Morf, ... 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 5 | 2018 |
| Design optimization of polyphase digital down converters for extremely high frequency wireless communications G Kim, R Capoccia, Y Leblebici 2015 IFIP/IEEE International Conference on Very Large Scale Integration …, 2015 | 5 | 2015 |
| Resistive random access memory based multiplexers and field programmable gate arrays PE Gaillardon, X Tang, G Kim, G De Micheli, E Giacomin US Patent 10,348,306, 2019 | 3 | 2019 |
| A time-division multiplexing signaling scheme for inter-symbol/channel interference reduction in low-power multi-drop memory links G Kim, C Cao, K Gharibdoust, A Tajalli, Y Leblebici IEEE Transactions on Circuits and Systems II: Express Briefs 64 (12), 1387-1391, 2017 | 3 | 2017 |
| Design and modeling of serial data transceiver architecture by employing multi-tone single-sideband signaling scheme G Kim, T Barailler, C Cao, K Gharibdoust, Y Leblebici IEEE Transactions on Circuits and Systems I: Regular Papers 64 (12), 3192-3201, 2017 | 3 | 2017 |
| A Digital Spectrum Shaping Signaling Serial-Data Transceiver with Crosstalk and ISI Reduction Property in Multi-Drop Interfaces G Kim, K Gharibdoust, A Tajalli, Y Leblebici IEEE Transactions on Circuits and Systems II: Express Briefs, 2016 | 3 | 2016 |
| A fully-digital spectrum shaping signaling for serial-data transceiver with crosstalk and ISI reduction property in multi-drop memory interfaces K Gharibdoust, G Kim, A Tajalli, Y Leblebici 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2905-2905, 2016 | 3 | 2016 |
| Far-End Crosstalk Cancellation With MIMO OFDM for> 200 Gb/s ADC-Based Serial Links G Kim IEEE Transactions on Circuits and Systems II: Express Briefs 70 (1), 81-85, 2022 | 2 | 2022 |
| Direct reconstruction of saturated samples in band-limited ofdm signals KH Jin, G Kim, Y Leblebici, JC Ye, M Unser arXiv preprint arXiv:1809.07188, 2018 | 2 | 2018 |
| Architectural Modeling of a Multi-Tone/Single-Sideband Serial Link Transceiver for Lossy Wireline Data Links G Kim, Y Leblebici 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2016), 2016 | 2 | 2016 |
| Architectural Modeling of a Single-Sideband Wireline Serial Data Transceiver for Multi-Drop I/O G Kim, Y Leblebici Proceedings of the IEEE 12th Conference on Ph. D. Research in …, 2016 | 2 | 2016 |
| A DAC/ADC-Based Wireline Transceiver Datapath Functional Verification On RFSoC Platform J Lee, S Jang, Y Choi, D Kim, S Yonar, M Braendli, A Ruffino, T Morf, ... IEEE Transactions on Circuits and Systems II: Express Briefs, 2024 | 1 | 2024 |
| An 8b 1.0-to-1.25 GS/s time-based ADC with bipolar VTC and sense amplifier latch interpolated gated ring oscillator TDC AS Yonar, PA Francese, M Brändli, M Kossel, M Prathapan, T Morf, ... IEEE Solid-State Circuits Letters, 2023 | 1 | 2023 |
Yusuf LeblebiciProfessor of Electrical Engineering, EPFL在 epfl.ch 的电子邮件经过验证
