| FPGA Implementation of 256-Bit, 64-Point DIT-FFT Using Radix-4 Algorithm P Brundavani Int. J. Adv. Res. Comput. Sci. Softw. Eng 3, 126-133, 2015 | 11 | 2015 |
| FPGA based wireless jamming networks NR Krishnaiah, P Brundavani International Journal of Modern Engineering Research 3 (4), 2567-71, 2013 | 3 | 2013 |
| Low static and dynamic power MTCMOS based 12T SRAM cell with recovery boosting M Tejeswar, P Brundavani International Journal of Innovative Research in Computer and Communication …, 2015 | 2 | 2015 |
| A Principal Component Analysis Algorithm for Seed Enterprise Financial Performance and Scientific and Technological Innovation P Brundavani Journal of Computer Allied Intelligence 2 (02), 49-62, 2024 | 1 | 2024 |
| Ffsgc-Based Classification of Environmental Factors in IOT Sports Education Data during the Covid-19 Pandemic P Brundavani, DV Vardhan, BA Raheem Journal of Sensors, IoT & Health Sciences (JSIHS, ISSN: 2584-2560) 2 (1), 28-54, 2024 | 1 | 2024 |
| A novel approach for minimising anti-aliasing effects in EEG data acquisition P Brundavani, DV Vardhan Open Life Sciences 18 (1), 20220664, 2023 | 1 | 2023 |
| Review of Low Power Techniques for Neural Recording Applications P Brundavani, D Vishnu Vardhan Modern Approaches in Machine Learning and Cognitive Science: A Walkthrough …, 2020 | 1 | 2020 |
| DESIGN AND IMPLEMENTATION OF LOW POWER 16-BIT ALU USING MGDI TECHNIQUE PB P SAI KRISHNA International Journal of VLSI System Design and Communication Syatems 5 (10 …, 2017 | 1* | 2017 |
| Robot Path Planning and Tracking with the Flower Pollination SearchOptimization Algorithm P Brundavani, Y Avanija Journal of Computer Allied Intelligence (JCAI, ISSN: 2584-2676) 2 (4), 70-81, 2024 | | 2024 |
| Second Order Continuous Time Incremental Sigma-Delta Modulator Based Analog-To-Digital Converter P Brundavani, DV Vardhan Design Engineering, 1013-1024, 2021 | | 2021 |
| 64 bit architecture implementation of dmc for s-ram using multiple redundant bits p brundavani subbarayudu IAETSD, 44-49, 2015 | | 2015 |
| hybrid dual dynamic pulsed flipflop p brundavani pavan kumar international journal of innovative research in computer and communication …, 2015 | | 2015 |
| prototyping embedded processor using iteration time based adaptive scheduling algorithm p brundavani usha rani nc'e-tides-12, 2012 | | 2012 |
| an efficient implementation of floating point multiplier p. brundavani m.sreekanth nc'e-tides-12, 2012 | | 2012 |
| low power h.264 video compression architectures for mobile communication r mahesh kumar p brundavani, k sreenivasa rao national conference on emerging trends in power, instrumentation …, 2010 | | 2010 |
| FIR FILTER DESIGN USING MCMA TECHNIQUE Y Balaji, P Brundavani | | |
| Comparison of neural signals P Brundavani | | |
| DESIGN AND ANALYSIS OF 16-BIT RISC PROCESSOR USING LOW POWER PIPELINE P Brundavani, DV Vardhan, P Mahesh, R Suresh | | |
