| A characterization of the Rodinia benchmark suite with comparison to contemporary CMP workloads S Che, JW Sheaffer, M Boyer, LG Szafaryn, L Wang, K Skadron IEEE International Symposium on Workload Characterization (IISWC'10), 1-11, 2010 | 418 | 2010 |
| CLEAR: Cross-Layer Exploration for Architecting Resilience - Combining hardware and software techniques to tolerate soft errors in processor cores E Cheng, S Mirkhani, LG Szafaryn, CY Cher, H Cho, K Skadron, MR Stan, ... Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 100 | 2016 |
| The resilience wall: Cross-layer solution strategies S Mitra, P Bose, E Cheng, CY Cher, H Cho, R Joshi, YM Kim, CR Lefurgy, ... Proceedings of Technical Program-2014 International Symposium on VLSI …, 2014 | 49 | 2014 |
| Experiences accelerating MATLAB systems biology applications LG Szafaryn, K Skadron, JJ Saucerman Proceedings of the Workshop on Biomedicine in Computing: Systems …, 2009 | 43 | 2009 |
| Evaluating overheads of multibit soft-error protection in the processor core LG Szafaryn, BH Meyer, K Skadron IEEE Micro 33 (4), 56-65, 2013 | 29 | 2013 |
| Tolerating soft errors in processor cores using clear (cross-layer exploration for architecting resilience) E Cheng, S Mirkhani, LG Szafaryn, CY Cher, H Cho, K Skadron, MR Stan, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 28 | 2017 |
| Experiences with achieving portability across heterogeneous architectures LG Szafaryn, T Gamblin, BR De Supinski, K Skadron Proceedings of WOLFHPC, in Conjunction with ICS, Tucson, 2011 | 19 | 2011 |
| Killi: Runtime fault classification to deploy low voltage caches without MBIST S Ganapathy, J Kalamatianos, BM Beckmann, S Raasch, LG Szafaryn 2019 IEEE International Symposium on High Performance Computer Architecture …, 2019 | 12 | 2019 |
| Trellis: Portability across architectures with a high-level framework LG Szafaryn, T Gamblin, BR De Supinski, K Skadron Journal of Parallel and Distributed Computing 73 (10), 1400-1413, 2013 | 8 | 2013 |
| Cross-layer resilience in low-voltage digital systems: key insights E Cheng, J Abraham, P Bose, A Buyuktosunoglu, K Campbell, D Chen, ... 2017 IEEE International Conference on Computer Design (ICCD), 593-596, 2017 | 6 | 2017 |
| CLEAR: Cross-Layer Exploration for Architecting Resilience E Cheng, S Mirkhani, LG Szafaryn, CY Cher, H Cho, K Skadron, MR Stan, ... Proceedings of the 53rd Annual Design Automation Conferenceon-DAC’16, 2016 | 3 | 2016 |
| Understanding and optimizing heterogeneous soft-error protection LG Szafaryn University of Virginia, 2015 | 1 | 2015 |
| Cross-Layer Resilience Exploration E Cheng, H Cho, S Mitra, LG Szafaryn, K Skadron, M Stan, CY Cher, ... | | |
| Experiences Porting MATLAB Systems Biology Applications to CUDA L Szafaryn, M Boyer, K Skadron | | |
| Evaluating the Overheads of Soft Error Protection Mechanisms in the Context of Multi-bit Errors at the Scope of a Processor Core LG Szafaryn, BH Meyer, K Skadron | | |
| EVALUATING OVERHEADS OF MULTIBIT SOFT-ERROR PROTECTION IN THE PROCESSOR CORE BH Meyer, LG Szafaryn, K Skadron | | |
| ASIC Design of FPCA Sub-Cores and Wrapper Infrastructure with LEON3 Platform P Wu, LG Szafaryn | | |
| Evaluating Soft Error Protection Mechanisms in the Context of Multi-bit Errors at the Scope of a Processor LG Szafaryn, B Meyer+, K Skadron | | |
| Application and Analysis of Output Prediction Logic to a 16-bit Carry Look Ahead Adder L Szafaryn, B Sheridan | | |
