| CompEx++: Compression-Expansion Coding for Energy, Latency, and Lifetime Improvements in MLC/TLC NVMs PM Palangappa, K Mohanram ACM Transactions on Architecture and Code Optimization (TACO) 14 (1), 30, 2017 | 88 | 2017 |
| CompEx: Compression-expansion coding for energy, latency, and lifetime improvements in MLC/TLC NVM PM Palangappa, K Mohanram 2016 IEEE International Symposium on High Performance Computer Architecture …, 2016 | 88 | 2016 |
| Compression architecture for bit-write reduction in non-volatile memory technologies DB Dgien, PM Palangappa, NA Hunter, J Li, K Mohanram Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale …, 2014 | 56 | 2014 |
| Flip-Mirror-Rotate: An architecture for bit-write reduction and wear leveling in non-volatile memories PM Palangappa, K Mohanram Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 221-224, 2015 | 36 | 2015 |
| WOM-code solutions for low latency and high endurance in phase change memory PM Palangappa, J Li, K Mohanram IEEE Transactions on Computers 65 (4), 1025-1040, 2015 | 22 | 2015 |
| Castle: Compression architecture for secure low latency, low energy, high endurance nvms PM Palangappa, K Mohanram Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 16 | 2018 |
| ECS: Error-correcting strings for lifetime improvements in nonvolatile memories S Swami, PM Palangappa, K Mohanram ACM Transactions on Architecture and Code Optimization (TACO) 14 (4), 1-29, 2017 | 16 | 2017 |
| Device, system and method for determining bit reliability information R Motwani, P Palangappa, S Vanaparthy US Patent 10,944,428, 2021 | 9 | 2021 |
| Techniques to use intrinsic information for a bit-flipping error correction control decoder A Bhatia, ZS Kwok, J Kang, PM Palangappa, SK Vanaparthy US Patent 11,146,289, 2021 | 8 | 2021 |
| Self-configuring error control coding PM Palangappa, RH Motwani US Patent 10,547,327, 2020 | 7 | 2020 |
| Estimating channel asymmetry for improved low-density parity check (ldpc) performance P Palangappa, RH Motwani US Patent App. 15/943,607, 2019 | 7 | 2019 |
| Die-wise residual bit error rate (RBER) estimation for memories PM Palangappa, RH Motwani, SK Vanaparthy US Patent 10,707,901, 2020 | 5 | 2020 |
| Memory circuit defect correction RH Motwani, ZS Kwok, PM Palangappa US Patent App. 14/998,240, 2017 | 5 | 2017 |
| Low density parity check (LDPC) decoder architecture with check node storage (CNS) or bounded circulant PM Palangappa, ZS Kwok US Patent 11,088,707, 2021 | 4 | 2021 |
| RAPID: Read acceleration for improved performance and endurance in MLC/TLC NVMs PM Palangappa, K Mohanram 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-7, 2018 | 4 | 2018 |
| Compressing error vectors for decoding logic to store compressed in a decoder memory used by the decoding logic PM Palangappa, ZS Kwok US Patent 11,063,607, 2021 | 3 | 2021 |
| Combating bit errors from stuck cells in flash memory using novel information theory techniques R Motwani, ZS Kwok, PM Palangappa 2018 International Conference on Computing, Networking and Communications …, 2018 | 1 | 2018 |
| Methods and apparatus for recommendation systems with anonymized datasets C Xue, J Zhang, PM Palangappa, RB Brufau, K Ding, RH Motwani, ... US Patent App. 18/395,311, 2024 | | 2024 |
| Methods and apparatus to construct graphs from coalesced features RH Motwani, K Ding, J Zhang, C Xue, PM Palangappa, RB Brufau, ... US Patent App. 18/545,762, 2024 | | 2024 |
| Methods and apparatuses for generating optimized LDPC codes R Motwani, P Palangappa, S Emmadi, SK Vanaparthy, A Bhatia US Patent 11,777,530, 2023 | | 2023 |
Kartik MohanramAssociate Professor of Electrical and Computer Engineering, University of Pittsburgh在 pitt.edu 的电子邮件经过验证
