| The impact of sequential-3D integration on semiconductor scaling roadmap A Mallik, A Vandooren, L Witters, A Walke, J Franco, Y Sherazi, P Weckx, ... 2017 IEEE International Electron Devices Meeting (IEDM), 32.1. 1-31.1. 4, 2017 | 56 | 2017 |
| Compact-2D: A physical design methodology to build commercial-quality face-to-face-bonded 3D ICs BW Ku, K Chang, SK Lim Proceedings of the 2018 International Symposium on Physical Design, 90-97, 2018 | 48 | 2018 |
| Compact-2D: A physical design methodology to build two-tier gate-level 3-D ICs BW Ku, K Chang, SK Lim IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 38 | 2019 |
| Shortest path and neighborhood subgraph extraction on a spiking memristive neuromorphic implementation CD Schuman, K Hamilton, T Mintz, MM Adnan, BW Ku, SK Lim, GS Rose Proceedings of the 7th Annual Neuro-inspired Computational Elements Workshop …, 2019 | 35 | 2019 |
| Physical design solutions to tackle FEOL/BEOL degradation in gate-level monolithic 3D ICs BW Ku, P Debacker, D Milojevic, P Raghavan, D Verkest, A Thean, ... Proceedings of the 2016 International Symposium on Low Power Electronics and …, 2016 | 21 | 2016 |
| Pseudo-3D approaches for commercial-grade RTL-to-GDS tool flow targeting monolithic 3D ICs H Park, BW Ku, K Chang, DE Shim, SK Lim Proceedings of the 2020 International Symposium on Physical Design, 47-54, 2020 | 20 | 2020 |
| Monolithic 3D IC design: Power, performance, and area impact at 7nm K Acharya, K Chang, BW Ku, S Panth, S Sinha, B Cline, G Yeric, SK Lim 2016 17th international symposium on quality electronic design (ISQED), 41-48, 2016 | 19 | 2016 |
| Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM Y Peng, BW Ku, Y Park, KI Park, SJ Jang, JS Choi, SK Lim Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 18 | 2015 |
| A twin memristor synapse for spike timing dependent learning in neuromorphic systems MM Adnan, S Sayyaparaju, GS Rose, CD Schuman, BW Ku, SK Lim 2018 31st IEEE International System-on-Chip Conference (SOCC), 37-42, 2018 | 17 | 2018 |
| How much cost reduction justifies the adoption of monolithic 3D ICs at 7nm node? BW Ku, P Debacker, D Milojevic, P Raghavan, SK Lim 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-7, 2016 | 16 | 2016 |
| Built-in self-test for inter-layer vias in monolithic 3D ICs A Chaudhuri, S Banerjee, H Park, BW Ku, K Chakrabarty, SK Lim 2019 IEEE European Test Symposium (ETS), 1-6, 2019 | 15 | 2019 |
| Design and architectural co-optimization of monolithic 3d liquid state machine-based neuromorphic processor BW Ku, Y Liu, Y Jin, S Samal, P Li, SK Lim Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 13 | 2018 |
| RTL-to-GDS tool flow and design-for-test solutions for monolithic 3D ICs H Park, K Chang, BW Ku, J Kim, E Lee, D Kim, A Chaudhuri, S Banerjee, ... Proceedings of the 56th Annual Design Automation Conference 2019, 1-4, 2019 | 10 | 2019 |
| Transistor-level monolithic 3D standard cell layout optimization for full-chip static power integrity BW Ku, T Song, A Nieuwoudt, SK Lim 2017 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2017 | 9 | 2017 |
| Built-in self-test and fault localization for inter-layer vias in monolithic 3D ICs A Chaudhuri, S Banerjee, J Kim, H Park, BW Ku, S Kannan, ... ACM Journal on Emerging Technologies in Computing Systems (JETC) 18 (1), 1-37, 2021 | 6 | 2021 |
| Pseudo-3d physical design flow for monolithic 3d ics: Comparisons and enhancements H Park, BW Ku, K Chang, DE Shim, SK Lim ACM Transactions on Design Automation of Electronic Systems (TODAES) 26 (5 …, 2021 | 6 | 2021 |
| ML-based wire rc prediction in monolithic 3d ics with an application to full-chip optimization SSK Pentapati, BW Ku, SK Lim Proceedings of the 2021 International Symposium on Physical Design, 75-82, 2021 | 5 | 2021 |
| Full-chip monolithic 3D IC design and power performance analysis with ASAP7 library K Chang, BW Ku, S Sinha, SK Lim 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD …, 2017 | 5 | 2017 |
| Simulating and estimating the behavior of a neuromorphic co-processor CD Schuman, R Pooser, T Mintz, MM Adnan, GS Rose, BW Ku, SK Lim Proceedings of the Second International Workshop on Post Moores Era …, 2017 | 5 | 2017 |
| Pin-in-the-middle: An efficient block pin assignment methodology for block-level monolithic 3d ics BW Ku, SK Lim Proceedings of the ACM/IEEE International Symposium on Low Power Electronics …, 2020 | 3 | 2020 |
