A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR Y Chiu, PR Gray, B Nikolic IEEE Journal of Solid-State Circuits 39 (12), 2139-2151, 2004 | 382 | 2004 |
Least mean square adaptive digital background calibration of pipelined analog-to-digital converters Y Chiu, CW Tsang, B Nikolic, PR Gray IEEE Transactions on Circuits and Systems I: Regular Papers 51 (1), 38-46, 2004 | 280 | 2004 |
A 12-bit, 45-MS/s, 3-mW redundant successive-approximation-register analog-to-digital converter with digital calibration W Liu, P Huang, Y Chiu IEEE Journal of Solid-State Circuits 46 (11), 2661-2672, 2011 | 268 | 2011 |
A 12b 22.5/45MS/s 3.0mW 0.059mm2 CMOS SAR ADC achieving over 90dB SFDR W Liu, P Huang, Y Chiu 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 380-381, 2010 | 210 | 2010 |
A 12 bit 160 MS/s two-step SAR ADC with background bit-weight calibration using a time-domain proximity detector Y Zhou, B Xu, Y Chiu IEEE Journal of Solid-State Circuits 50 (4), 920-931, 2015 | 139 | 2015 |
A 600MS/s 30mW 0.13 µm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization W Liu, Y Chang, SK Hsien, BW Chen, YP Lee, WT Chen, TY Yang, GK Ma, ... 2009 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2009 | 109 | 2009 |
Scaling of analog-to-digital converters into ultra-deep-submicron CMOS Y Chiu, B Nikolic, PR Gray Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005 …, 2005 | 100 | 2005 |
A non-interleaved 12-b 330-MS/s pipelined-SAR ADC with PVT-stabilized dynamic amplifier achieving sub-1-dB SNDR variation H Huang, H Xu, B Elies, Y Chiu IEEE Journal of Solid-State Circuits 52 (12), 3235-3247, 2017 | 92 | 2017 |
Inherently linear capacitor error-averaging techniques for pipelined A/D conversion Y Chiu IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2000 | 80 | 2000 |
A fast digital predistortion algorithm for radio-frequency power amplifier linearization with loop delay compensation H Li, DH Kwon, D Chen, Y Chiu IEEE Journal of selected topics in signal processing 3 (3), 374-383, 2009 | 79 | 2009 |
Broad-band electronic linearizer for externally modulated analog fiber-optic links Y Chiu, B Jalali, S Garner, W Steier IEEE Photonics Technology Letters 11 (1), 48-50, 1999 | 79 | 1999 |
A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration W Liu, P Huang, Y Chiu Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 1-4, 2012 | 75 | 2012 |
A skew-free 10 GS/s 6 bit CMOS ADC with compact time-domain signal folding and inherent DEM S Zhu, B Xu, B Wu, K Soppimath, Y Chiu IEEE Journal of Solid-State Circuits 51 (8), 1785-1796, 2016 | 74 | 2016 |
Background ADC calibration in digital domain C Tsang, Y Chiu, J Vanderhaegen, S Hoyos, C Chen, R Brodersen, ... 2008 IEEE Custom Integrated Circuits Conference, 301-304, 2008 | 66 | 2008 |
A 23-mW 24-GS/s 6-bit voltage-time hybrid time-interleaved ADC in 28-nm CMOS B Xu, Y Zhou, Y Chiu IEEE Journal of Solid-State Circuits 52 (4), 1091-1100, 2017 | 64 | 2017 |
SHA-less pipelined ADC with in situ background clock-skew calibration P Huang, S Hsien, V Lu, P Wan, SC Lee, W Liu, BW Chen, YP Lee, ... IEEE Journal of Solid-State Circuits 46 (8), 1893-1903, 2011 | 61 | 2011 |
A 2-GS/s 8-bit non-interleaved time-domain flash ADC based on remainder number system in 65-nm CMOS S Zhu, B Wu, Y Cai, Y Chiu IEEE Journal of Solid-State Circuits 53 (4), 1172-1183, 2017 | 59 | 2017 |
OFDM receiver design Y Chiu, D Markovic, H Tang, N Zhang EE225C VLSI Signal Porcessing Fall 2000, 2000 | 59 | 2000 |
A 12-b 1-GS/s 31.5-mW time-interleaved SAR ADC with analog HPF-assisted skew calibration and randomly sampling reference ADC Y Zhou, B Xu, Y Chiu IEEE Journal of Solid-State Circuits 54 (8), 2207-2218, 2019 | 54 | 2019 |
A 1.8 V 14 b 10 MS/s pipelined ADC in 0.18/spl mu/m CMOS with 99 dB SFDR Y Chiu, PR Gray, B Nikolic 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No …, 2004 | 53 | 2004 |