An 8T Low-Voltage and Low-Leakage Half-Selection Disturb-Free SRAM Using Bulk-CMOS and FinFETs G Pasandi, SM Fakhraie IEEE Transactions on Electron Devices 61 (7), 2357- 2363, 2014 | 101 | 2014 |
A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations G Pasandi, SM Fakhraie IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015 | 96 | 2015 |
NISQ+: Boosting quantum computing power by approximating quantum error correction A Holmes, MR Jokar, G Pasandi, Y Ding, M Pedram, FT Chong 2020 ACM/IEEE 47th annual international symposium on computer architecture …, 2020 | 88 | 2020 |
Chipnemo: Domain-adapted llms for chip design M Liu, TD Ene, R Kirby, C Cheng, N Pinckney, R Liang, J Alben, H Anand, ... arXiv preprint arXiv:2311.00176, 2023 | 60 | 2023 |
PBMap: A Path Balancing Technology Mapping Algorithm for Single Flux Quantum Logic Circuits G Pasandi, M Pedram IEEE Transactions on Applied Superconductivity 29 (4), 2018 | 56 | 2018 |
SFQmap: A technology mapping tool for single flux quantum logic circuits G Pasandi, A Shafaei, M Pedram 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 45 | 2018 |
Energy-efficient, low-latency realization of neural networks through boolean logic minimization M Nazemi, G Pasandi, M Pedram Proceedings of the 24th Asia and South Pacific design automation conference …, 2019 | 44 | 2019 |
A new sub-threshold 7T SRAM cell design with capability of bit-interleaving in 90 nm CMOS G Pasandi, SM Fakhraie 2013 21st Iranian conference on electrical engineering (ICEE), 1-6, 2013 | 42 | 2013 |
An efficient pipelined architecture for superconducting single flux quantum logic circuits utilizing dual clocks G Pasandi, M Pedram IEEE Transactions on Applied Superconductivity 30 (2), 1-12, 2019 | 29 | 2019 |
DigiQ: A scalable digital controller for quantum computers using SFQ logic MR Jokar, R Rines, G Pasandi, H Cong, A Holmes, Y Shi, M Pedram, ... 2022 IEEE International Symposium on High-Performance Computer Architecture …, 2022 | 25 | 2022 |
Approximate logic synthesis: A reinforcement learning-based technology mapping approach G Pasandi, S Nazarian, M Pedram 20th International Symposium on Quality Electronic Design (ISQED), 26-32, 2019 | 25 | 2019 |
A dynamic programming-based, path balancing technology mapping algorithm targeting area minimization G Pasandi, M Pedram 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019 | 23 | 2019 |
Internal write‐back and read‐before‐write schemes to eliminate the disturbance to the half‐selected cells in SRAMs G Pasandi, M Pedram IET Circuits, Devices & Systems 12 (4), 460-466, 2018 | 22 | 2018 |
Nullanet: Training deep neural networks for reduced-memory-access inference M Nazemi, G Pasandi, M Pedram arXiv preprint arXiv:1807.08716, 2018 | 20 | 2018 |
Balanced factorization and rewriting algorithms for synthesizing single flux quantum logic circuits G Pasandi, M Pedram Proceedings of the 2019 on Great Lakes Symposium on VLSI, 183-188, 2019 | 16 | 2019 |
A new low-power 10T SRAM cell with improved read SNM G Pasandi, M Jafari, M Imani International Journal of Electronics 102 (10), 1621-1633, 2015 | 16 | 2015 |
Deep-PowerX: A deep learning-based framework for low-power approximate logic synthesis G Pasandi, M Peterson, M Herrera, S Nazarian, M Pedram Proceedings of the ACM/IEEE International Symposium on Low Power Electronics …, 2020 | 15 | 2020 |
Sport lab sfq logic circuit benchmark suite N Katam, SN Shahsavani, TR Lin, G Pasandi, A Shafaei, M Pedram Univ. Southern California, Los Angeles, CA, USA, Tech. Rep, 2017 | 14 | 2017 |
A new sub-300mv 8T SRAM cell design in 90nm CMOS G Pasandi, SM Fakhraie The 17th CSI International Symposium on Computer Architecture & Digital …, 2013 | 13 | 2013 |
A new low-leakage T-Gate based 8T SRAM cell with improved write-ability in 90nm CMOS technology G Pasandi, E Qasemi, SM Fakhraie 2014 22nd Iranian Conference on Electrical Engineering (ICEE), 382-386, 2014 | 11 | 2014 |