| Timing characterization of clock buffers for clock tree synthesis C Sitik, S Lerner, B Taskin 2014 IEEE 32nd International Conference on Computer Design (ICCD), 230-236, 2014 | 15 | 2014 |
| Resonant clock synchronization with active silicon interposer for multi-die systems R Kuttappa, B Taskin, S Lerner, V Pano IEEE Transactions on Circuits and Systems I: Regular Papers 68 (4), 1636-1645, 2021 | 13 | 2021 |
| Workload-aware routing (WAR) for network-on-chip lifetime improvement V Pano, S Lerner, I Yilmaz, M Lui, B Taskin 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 13 | 2018 |
| Workload-aware ASIC flow for lifetime improvement of multi-core IoT processors S Lerner, B Taskin 2017 18th International Symposium on Quality Electronic Design (ISQED), 379-384, 2017 | 11 | 2017 |
| Robust low power clock synchronization for multi-die systems R Kuttappa, B Taskin, S Lerner, V Pano, I Savidis 2019 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2019 | 9 | 2019 |
| Stability of rotary traveling wave oscillators under process variations and NBTI R Kuttappa, L Filippini, S Lerner, B Taskin 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 8 | 2017 |
| Can you trust your memory trace? A comparison of memory traces from binary instrumentation and simulation S Nilakantan, S Lerner, M Hempstead, B Taskin 2015 28th International Conference on VLSI Design, 135-140, 2015 | 7 | 2015 |
| Custard: ASIC workload-aware reliable design for multicore IoT processors S Lerner, I Yilmaz, B Taskin IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (3), 700-710, 2018 | 5 | 2018 |
| Slew merging region propagation for bounded slew and skew clock tree synthesis S Lerner, B Taskin IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (1), 1-10, 2018 | 4 | 2018 |
| Slew-down: analysis of slew relaxation for low-impact clock buffers S Lerner, E Leggett, B Taskin 2017 ACM/IEEE International Workshop on System Level Interconnect Prediction …, 2017 | 4 | 2017 |
| Low Swing—Low Frequency Rotary Traveling Wave Oscillators R Kuttappa, S Lerner, L Filippini, B Taskin 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 3 | 2019 |
| NoC router lifetime improvement using per-port router utilization S Lerner, V Pano, B Taskin 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 3 | 2018 |
| Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis S Lerner, B Taskin 2018 Ninth International Green and Sustainable Computing Conference (IGSC), 1-6, 2018 | 1 | 2018 |
| WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS S Lerner, B Taskin 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 465-470, 2017 | 1 | 2017 |
| Design Automation for Charge Recovery Logic YE Gonul, L Filippini, J Oh, R Kuttappa, S Lerner, M Kaneko, B Taskin 2024 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2024 | | 2024 |
| Bounded and Variation-Aware Design for Clock Tree Synthesis SP Lerner Drexel University, 2024 | | 2024 |
| Traveling With Diabetes: Planning the Right Moves E Quattrocchi, S Lerner US PHARMACIST, 38-42, 2004 | | 2004 |
