| Fabrication and characterization of a thin-body poly-Si 1T DRAM with charge-trap effect JH Seo, YJ Yoon, E Yu, W Sun, H Shin, IM Kang, JH Lee, S Cho IEEE Electron Device Letters 40 (4), 566-569, 2019 | 38 | 2019 |
| Three-dimensional (3D) vertical resistive random-access memory (VRRAM) synapses for neural network systems W Sun, S Choi, B Kim, J Park Materials 12 (20), 3451, 2019 | 17 | 2019 |
| A new bias scheme for a low power consumption ReRAM crossbar array W Sun, S Choi, H Shin Semiconductor Science and Technology 31 (8), 085009, 2016 | 17 | 2016 |
| Analysis of stress-induced mobility enhancement on (100)-oriented single-and double-gate n-MOSFETs using silicon-thickness-dependent deformation potential S Choi, W Sun, H Shin Semiconductor Science and Technology 30 (4), 045009, 2015 | 16 | 2015 |
| Memristor neural network training with clock synchronous neuromorphic system S Jo, W Sun, B Kim, S Kim, J Park, H Shin Micromachines 10 (6), 384, 2019 | 15 | 2019 |
| Optimization of uniaxial stress for high electron mobility on biaxially-strained n-MOSFETs W Sun, H Shin Solid-State Electronics 94, 23-27, 2014 | 14 | 2014 |
| A novel hardware security architecture for IoT device: PD-CRP (PUF database and challenge–response pair) bloom filter on memristor-based PUF J Lee, S Choi, D Kim, Y Choi, W Sun Applied Sciences 10 (19), 6692, 2020 | 13 | 2020 |
| ReRAM crossbar array: Reduction of access time by reducing the parasitic capacitance of the selector device H Lim, W Sun, H Shin IEEE Transactions on Electron Devices 63 (2), 873-876, 2016 | 13 | 2016 |
| A hardware security architecture: PUFs (physical unclonable functions) using memristor W Sun, J Lee, D Kim, Y Choi 2021 IEEE Region 10 Symposium (TENSYMP), 1-4, 2021 | 12 | 2021 |
| Analysis of the sensing margin of silicon and poly-Si 1T-DRAM H Kim, S Yoo, IM Kang, S Cho, W Sun, H Shin Micromachines 11 (2), 228, 2020 | 12 | 2020 |
| Analysis of read margin and write power consumption of a 3-D vertical RRAM (VRRAM) crossbar array S Choi, W Sun, H Shin IEEE Journal of the Electron Devices Society 6, 1192-1196, 2018 | 11 | 2018 |
| Selected bit-line current puf: implementation of hardware security primitive based on a memristor crossbar array D Kim, TH Kim, Y Choi, GH Lee, J Lee, W Sun, BG Park, H Kim, H Shin IEEE Access 9, 120901-120910, 2021 | 8 | 2021 |
| Multibit-generating pulsewidth-based memristive-puf structure and circuit implementation S Choi, D Kim, Y Choi, W Sun, H Shin Electronics 9 (9), 1446, 2020 | 8 | 2020 |
| Analysis of operation characteristics of junctionless poly-Si 1T-DRAM in accumulation mode H Kim, IM Kang, S Cho, W Sun, H Shin Semiconductor Science and Technology 34 (10), 105007, 2019 | 8 | 2019 |
| Semiconductor device having a vertical transistor and method for manufacturing the same WK Sun US Patent 7,592,643, 2009 | 8 | 2009 |
| Analysis of the memristor-based crossbar synapse for neuromorphic systems B Kim, S Jo, W Sun, H Shin Journal of nanoscience and nanotechnology 19 (10), 6703-6709, 2019 | 7 | 2019 |
| A compact model of gate-voltage-dependent quantum effects in short-channel surrounding-gate metal-oxide-semiconductor field-effect transistors JH Kim, WK Sun, SH Park, HI Lim, HS Shin JSTS: Journal of Semiconductor Technology and Science 11 (4), 278-286, 2011 | 7 | 2011 |
| Analysis of cell variability impact on a 3-D vertical RRAM (VRRAM) crossbar array using a modified lumping method S Choi, W Sun, H Shin IEEE Transactions on Electron Devices 66 (1), 759-765, 2018 | 5 | 2018 |
| Saddle-fin cell transistors with oxide etch rate control by using tilted ion implantation (TIS-Fin) for sub-50-nm DRAMs MS Yoo, KS Choi, WK Sun Journal of the Korean Physical Society 56, 2010 | 5 | 2010 |
| Effects of shallow trench isolation on silicon-on-insulator devices for mixed signal processing H Lee, YJ Park, HS Min, JH Lee, H Shin, W Sun, DG Kang Journal of the Korean Physical Society 40 (4), 653-657, 2002 | 5 | 2002 |
