| BlueSentinel: a first approach using iBeacon for an energy efficient occupancy detection system. G Conte, M De Marchi, AA Nacci, V Rana, D Sciuto BuildSys@ SenSys, 11-19, 2014 | 178 | 2014 |
| A mapping flow for dynamically reconfigurable multi-core system-on-chip design I Beretta, V Rana, D Atienza, D Sciuto IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011 | 110 | 2011 |
| Partial dynamic reconfiguration in a multi-fpga clustered architecture based on linux V Rana, M Santambrogio, D Sciuto, B Kettelhoit, M Koester, M Porrmann, ... 2007 IEEE International Parallel and Distributed Processing Symposium, 1-8, 2007 | 50 | 2007 |
| A real-time information system for public transport in case of delays and service disruptions M Bruglieri, F Bruschi, A Colorni, A Luè, R Nocerino, V Rana Transportation Research Procedia 10, 493-502, 2015 | 47 | 2015 |
| A reconfigurable network-on-chip architecture for optimal multi-processor SoC communication V Rana, D Atienza, MD Santambrogio, D Sciuto, G De Micheli VLSI-SoC: Design Methodologies for SoC and SiP: 16th IFIP WG 10.5/IEEE …, 2010 | 46 | 2010 |
| Dynamic reconfigurability in embedded system design V Rana, M Santambrogio, D Sciuto 2007 IEEE International Symposium on Circuits and Systems (ISCAS), 2734-2737, 2007 | 45 | 2007 |
| BuildingRules: A Trigger-Action--Based System to Manage Complex Commercial Buildings AA Nacci, V Rana, B Balaji, P Spoletini, R Gupta, D Sciuto, Y Agarwal ACM Transactions on Cyber-Physical Systems 2 (2), 1-22, 2018 | 43 | 2018 |
| Operating system support for online partial dynamic reconfiguration management MD Santambrogio, V Rana, D Sciuto 2008 International Conference on Field Programmable Logic and Applications …, 2008 | 41 | 2008 |
| A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices AA Nacci, V Rana, F Bruschi, D Sciuto, I Beretta, D Atienza Proceedings of the 50th annual design automation conference, 1-6, 2013 | 39 | 2013 |
| B²IRS: A Technique to Reduce BAN-BAN Interferences in Wireless Sensor Networks PR Grassi, V Rana, I Beretta, D Sciuto 2012 Ninth International Conference on Wearable and Implantable Body Sensor …, 2012 | 32 | 2012 |
| A novel soc design methodology combining adaptive software and reconfigurable hardware MD Santambrogio, V Rana, SO Memik, UA Acar, D Sciuto 2007 IEEE/ACM International Conference on Computer-Aided Design, 303-308, 2007 | 26 | 2007 |
| A hybrid mapping-scheduling technique for dynamically reconfigurable hardware JA Clemente, V Rana, D Sciuto, I Beretta, D Atienza 2011 21st International Conference on Field Programmable Logic and …, 2011 | 24 | 2011 |
| Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems V Rana, S Murali, D Atienza, MD Santambrogio, L Benini, D Sciuto Proceedings of the 7th IEEE/ACM international conference on Hardware …, 2009 | 24 | 2009 |
| An embedded Gabor-based palm vein recognition system P Cancian, GW Di Donato, V Rana, MD Santambrogio 2017 IEEE EMBS International Conference on Biomedical & Health Informatics …, 2017 | 21 | 2017 |
| An efficient quantum-dot cellular automata adder F Bruschi, F Perini, V Rana, D Sciuto 2011 Design, Automation & Test in Europe, 1-4, 2011 | 21 | 2011 |
| A mapping-scheduling algorithm for hardware acceleration on reconfigurable platforms JA Clemente, I Beretta, V Rana, D Atienza, D Sciuto ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 (2), 1-27, 2014 | 20 | 2014 |
| A generation flow for self-reconfiguration controllers customization A Cuoccio, PR Grassi, V Rana, MD Santambrogio, D Sciuto 4th IEEE International Symposium on Electronic Design, Test and Applications …, 2008 | 20 | 2008 |
| Model-based design for wireless body sensor network nodes I Beretta, F Rincon, N Khaled, PR Grassi, V Rana, D Atienza, D Sciuto 2012 13th Latin American Test Workshop (LATW), 1-6, 2012 | 19 | 2012 |
| Reconfigurable NoC design flow for multiple applications run-time mapping on FPGA devices D Cozzi, C Farè, A Meroni, V Rana, MD Santambrogio, D Sciuto Proceedings of the 19th ACM Great Lakes symposium on VLSI, 421-424, 2009 | 17 | 2009 |
| VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow F Ferrandi, G Ferrara, R Palazzo, V Rana, MD Santambrogio Proceedings 20th IEEE International Parallel & Distributed Processing …, 2006 | 17 | 2006 |
Marco Domenico SantambrogioAssociate professor, Politecnico di Milano在 polimi.it 的电子邮件经过验证
